32results about How to "Increase reverse blocking voltage" patented technology

This invention discloses a junction barrier Schottky device supported on a substrate that has a first conductivity type. The Schottky device includes a first diffusion region of a fist conductivity type for functioning as a forward barrier height reduction region. The Schottky device further includes a second diffusion region of a second conductivity type disposed immediately adjacent to the first diffusion region for functioning as a backward blocking enhancement region to reduce the backward leakage current.

The invention relates to a grooved semiconductor rectifier and a manufacturing method thereof. The grooved semiconductor rectifier comprises a semiconductor baseplate, a first conduction type substrate and a first conduction type drift region, wherein one or more grooves extend from the first main plane to the first conduction type drift region, one or more mesa parts are limited at the upper part of the first conduction type drift region, and the upper part of the mesa part is provided with a first conduction type injection layer; the inner wall of the groove is covered with an insulation oxide layer, and a first electrode is deposited in the groove covered with the insulation oxide layer; the first conduction type drift region is provided with a second conduction type enclosure layer corresponding to the bottom of the groove, and the bottom of the groove is coated by the second conduction type enclosure layer; a first metal layer corresponding to the upper part of the first plane is deposited on the semiconductor baseplate; and the second plane of the semiconductor baseplate is covered with a second metal layer. The invention has the advantage of low manufacturing cost, and reduces the reverse leakage current and the forward conduction voltage drop of the Schottky rectifier.

An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided.

The invention discloses a hetetrostructure field effect diode and a manufacturing method thereof. The hetetrostructure field effect diode comprises a substrate as well as an insulation high-resistance semiconductor and a wide bandgap hetetrostructure barrier layer which are sequentially arranged on the substrate, wherein the insulation high-resistance semiconductor and the wide bandgap hetetrostructure barrier layer form a two-dimensional electron gas hetetrostructure epitaxial layer, an isolated table board is formed at the top of the insulation high-resistance semiconductor and the wide bandgap hetetrostructure barrier layer, an insulating medium layer is formed on the isolated table board, a cathode electrode and an anode electrode which are contacted with the wide bandgap hetetrostructure barrier layer are respectively formed on the insulating medium layer, wherein one part of the anode electrode is arranged on the wide bandgap hetetrostructure barrier layer, the other part of the anode electrode is arranged on the insulating medium layer to form a diode anode provided with a Schottky-MIS (metal-insulator-semiconductor) dual-structure electrode, and the anode electrode is made from a low-work function metal. According to the invention, the characteristics of low forward on voltage, low reverse leakage current and high reverse blocking voltage can be realized, thus, the method in the invention is applicable to manufacturing of a power type GaN-base hetetrostructure field effect diode.

A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p⁺-type separation region 24 is formed on the side wall of trench 23 such that p⁺-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.

A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.

The invention relates to a lateral bipolar transistor with a composite structure. The lateral bipolar transistor particularly comprises a substrate and a first RESURF zone arranged on the substrate, as well as a current collection zone, a base zone and an emission zone which are arranged in sequence, and further comprises a second RESURF zone used for smoothing the change of the electric field of a drift zone and a plurality of floating rings formed at the periphery of the ohmic contact zone of the current collection zone, wherein an emitting electrode is arranged on the emission zone; the floating rings are positioned on the surface of the current collection zone and close to the ohmic contact zone; through the arrangement of the second RESURF zone, the electric field of the drift zone of the lateral bipolar transistor becomes smooth, and the specific on resistance of the whole device is further reduced; space charges of the floating rings are connected into a whole with a space charge in the drift zone of the current collection zone, so that the space charge area of the drift zone is increased, gathering of the space field at the edge of the ohmic contact zone of the current collection zone is greatly reduced, and under the condition of the same length of the drift zone, higher blocking voltage can be born.

The invention relates to a manufacturing method of a power diode and the power diode. According to the method, an N-type epitaxial layer is prepared on a semiconductor substrate; a silicon oxide layer and a polysilicon layer are sequentially prepared at the upper part of the N-type epitaxial layer; preset positions of the silicon oxide layer and the polysilicon layer are etched to form a groove in contact with the N-type epitaxial layer; a P-type ion implantation region and an N-type ion implantation region are formed in the N-type epitaxial layer to form an NPN structure; a metal layer is formed at the upper part of the polysilicon layer; and the metal layer is taken as an anode of the power diode. The power diode provided by the invention is relatively high in reverse blocking voltage, the on-state voltage drop is smaller than that of the diode with a traditional structure, the reverse recovery time is relatively short and the leakage current level is much smaller than that of a traditional device. The NPN structure is formed by controlling the groove and a dielectric side wall of the groove in production technology; the technology is relatively simple; and the manufacturing cost of the device is reduced.

The invention provides a laterally diffused MOS device. The device comprises a first conductive type semiconductor substrate, a first conductive type semiconductor body region, a second conductive type semiconductor drift region, a second conductive type semiconductor source region, a highly-doped first conductive type semiconductor body contact region, a gate structure, wherein the gate structurecomprises a polysilicon gate electrode and a gate oxide layer; at least two polysilicon islands are arranged on the upper surface of the interior of the second conductive type semiconductor drift region, and uniformly-distributed charges are stored in the polysilicon islands; and the distance from the bottom of the polysilicon islands to the first conductive type semiconductor substrate is increased gradually in the direction from the first conductive type semiconductor body region to a second conductive type semiconductor drain region. By setting the multiple polysilicon islands of differentdepths and for storing charges in the drift region, and by changing the charge quantity and the width of the drift region needing to be depleted, the electric field distribution in the drift region is more uniform, and the reverse blocking voltage of the device is improved.

In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N⁺ substrate, a N-type layer, a silicon dioxide layer and a P⁺ layer. The N⁺ substrate is disposed under the P-type layer. The N-type layer is disposed on the N+ substrate. The silicon dioxide layer is disposed between the N-type layer and the P-type layer. The P⁺ layer is disposed on the P-type layer and the N-type layer.

The invention relates to an LDMOS device with multiple trenches, and belongs to the technical field of power semiconductors. According to the LDMOS device with multiple trenches, the morphology of a second conductive type diffusion region is changed through trench etching, and uniformly distributed doping is realized, so that the electric field distribution of the surface is optimized, the area ofa drift region is reduced, the morphology of junctions on two sides is improved, the reverse blocking voltage of the device is improved, and the on resistance can be improved at the same time.

The invention provides a diode preparation method and a diode. The diode preparation method comprises the steps of: sequentially forming a gate oxide layer, a polycrystalline silicon layer and an isolated oxide layer on an N-type substrate on which an N-type epitaxial layer is formed; adopting an isotropic corrosion technology for etching the isolated oxide layer; performing anisotropic etching on the polycrystalline silicon layer and the gate oxide layer based on a patterned mask in sequence, and etching a specified thickness of the N-type epitaxial layer continuously; removing the patterned mask to expose injection reserved regions of the polycrystalline silicon layer, and forming P-type body regions in the N-type epitaxial layer by means of injection windows; forming P-type channels in the N-type epitaxial layer under the injection reserved regions; removing the isolated oxide layer; and forming a metal electrode on the N-type substrate on which the isolated oxide layer is removed, so as to complete the preparation of the diode. By adopting the diode preparation method, the prepared diode has the advantages of low potential barrier, small reverse current, short reverse recovery time, high reverse blocking voltage and low conduction voltage drop.

The invention relates to the semiconductor technology and particularly relates to a metal oxide semiconductor diode with high voltage withstanding and low conduction voltage drop characteristics. The metal oxide semiconductor diode comprises an electron accumulation layer structure and a junction field effect transistor structure and can obtain low conduction voltage drop. At the same time, an N type area 3 with a high doping concentration is employed, and the conduction voltage drop of the diode in positive conduction is reduced further. When a device is reversely blocked, the acceptor impurities contained in a P type area 8 and a P type buried layer 8 and the donor impurity contained in the N type area are mutually depleted, thus the electric field distribution of a drift area is in a rectangular distribution, and the reverse blocking voltage of the device can be raised. Therefore, the new structure of the invention has the advantages of high voltage withstanding and low conduction voltage drop.