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82results about How to "More area" patented technology

Process for forming both split gate and common gate finfet transistors and integrated circuits therefrom

A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height. Gate slacks are formed on the taller and shorter fins such that a gate electrode for the taller fin is a split gate electrode and a gate electrode for the shorter fin is a common gate electrode. Fabrication of the IC is completed, wherein the split gate FinFET includes the split gate electrode and the common gate FinFET device includes the common gate electrode. An IC includes a substrate having a semiconductor surface, a plurality of semiconductor fins including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height, and at least one common gate FinFET device formed from the shorter fin and at least one split gate FinFET device providing a parallel gate transistor pair comprising a first and a second transistor formed from the taller fin.
Owner:TEXAS INSTR INC

Data processing apparatus and method for handling instructions to be executed by processing circuitry

A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
Owner:ARM LTD
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