A repair circuit and a method of repairing defects in a
semiconductor memory device are disclosed. The repair circuit of a
semiconductor memory device includes an address
generating unit, an address electrical fuse (e-fuse) box unit, a row / column selecting e-fuse unit, a row repair
control unit, and a column repair
control unit. The address
generating unit generates a row address or a column address in response to a
control signal, the address e-fuse box unit stores a defective address after packaging, and the row / column selecting e-fuse unit generates a select
signal for determining whether the defective address corresponds to a row defect or a column defect. The row repair
control unit compares the defective address after packaging with the row address in response to a first state of the select
signal, and the column repair control unit compares the defective address after packaging with the column address in response to a second state of the select
signal.