This application relates to a hardware scheduling device, task scheduling method,
system,
chip, and electronic device. The hardware scheduling device includes on-
chip memory, multiple hardware
processing units, and an arbitrator. The multiple hardware
processing units are all connected to the on-
chip memory and are used to read
scheduling instructions from the on-chip memory and send
scheduling instructions. The
scheduling instructions are used to schedule a subsystem in an
image signal processor, so that the subsystem responds to the scheduling instructions and processes the corresponding task. The arbitrator is connected between each hardware
processing unit and the
image signal processor, and is used to arbitrate the scheduling instructions received simultaneously from each hardware processing unit, determine the target scheduling instruction, and send the target scheduling instruction to the
image signal processor via a transmission
bus. Using the above-mentioned hardware scheduling device, the entire scheduling process is completed in hardware, the scheduling
delay has a high degree of
determinism, effectively reducing the communication
delay of
signal reception and transmission, and meeting the requirements of real-time tasks.