77 results about "Nonlinear capacitance" patented technology

A storage pixel sensor disposed on a semiconductor substrate comprises a photosensor. At least one nonlinear capacitive element is coupled to the photosensor. At least one nonlinear capacitive element is arranged to have a compressive photocharge-to-voltage gain function. An amplifier has an input coupled to the nonlinear capacitor and an output. Other, non-capacitive elements may be employed to produce a compressive photo-charge-to-voltage gain having at least one breakpoint.

A method for making metal-insulator-metal (MIM) capacitors having insulators with high-dielectric-constant and sandwiched between wide-band-gap insulators resulting in low leakage currents and high capacitance per unit area is achieved. The high-k layer increases the capacitance per unit area for next generation mixed-signal devices while the wide-band-gap insulators reduce leakage currents. In a second embodiment, a multilayer of different high-k materials is formed between the wide-band-gap insulators to substantially increase the capacitance per unit area. The layer materials and thicknesses are optimized to reduce the nonlinear capacitance dependence on voltage.

An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction.

Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

The application discloses an adaptive biasing radio frequency power amplifier comprising a biasing circuit and a power level amplifying circuit. The biasing circuit is used for providing dynamic bias voltage for a transistor II in the power level amplifying circuit; the work voltage I is connected to one end of a resistor I; the other end of the resistor I is used as an output end of the biasing circuit; the work voltage II is connected to the anode of a diode I; the cathode of the diode I is connected to the output end of the biasing circuit; the value of the work voltage II makes the diode I in a default critical conduction status. the power level amplifying circuit comprises a transistor I and the transistor II, which adopt common source and common gate structures; the transistor I adopts common source connection and the grid of the transistor I receives radio frequency input signals; the transistor II adopts common grade connection and the drain electrode of the transistor II outputs drain voltage II. The application provides adaptive biasing voltage postponing gain compression and reducing phase distortion caused by non-linear capacity.

A wireless-power-transfer system includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a primary series-resonant capacitor connected to an oscillator-controlled drive stage that provides fixed-frequency output and a transmitting coil connected to the primary series-resonant capacitor. The transmitting resonant frequency is below the fixed frequency of the oscillator-controlled drive stage. The receiver circuit includes a receiving coil, a secondary series-resonant capacitor connected in series with the receiving coil, and a secondary parallel-resonant capacitor connected in parallel with the receiving coil. The receiving resonant frequency increases as a nonlinear capacitance of the at least one rectifier decreases when the rectifier-circuit DC output increases.

This invention discloses an anti-ferroelectric ceramic capacitor material and its preparation technology, which applies Sn of positive four valency to replace Zr of positive 4 valency, applies the positive 3 valency La to replace 2 valency Pb in the compound of Pb(Zr, Ti) O3 to form a multi-component solid solution with Pb vacancy. The balanced formula of the charge and the valency is: (Pb1-3 2/2Laz)[(Zri-ysny)1-Tix]O3, in which, x varies between 0.06`0.20, y: 0.2010.40, z varies between 0.02-0.08, or positive 2 valency Sr or Ba is added to replace 2 valency Pb in Pb(zr, Ti) O3, the formula is [(Pb1-wBw)1-3z/2Laz][Zr1-ySny]1-xTix ]O3, B expresses Sr or Ba of 2 valency, w varies between 0.02-0.12. A conventional electronic ceramic preparation method is applied in the method.

A circuit block which comprises a non-linear capacitor with two different values of capacitance dependent on a value of a voltage of a resonant signal on the capacitor; a plurality of second capacitors each coupled to a respective switch to enable a said second capacitor to be switched in or out of parallel connection with the nonlinear capacitor; and a tuning control, coupled to the second capacitor switches, and sensing an amplitude of the resonant signal. The tuning control circuit is configured to control the second capacitor switches to successively switch the second capacitors in/out of parallel connection with the non-linear capacitor dependent on the amplitude of the resonant signal until the non-linear capacitor has substantially a single one of two different values, such that in a resonant circuit the circuit block then behaves as a fixed value capacitor.

In one implementation, a power amplifier may include a gain device to receive an input signal and to output an amplified signal, and a compensation device coupled to the gain device to compensate for a change in a capacitance of the gain device occurring due to a change in the input signal. The power amplifier may be formed using a complementary metal oxide semiconductor (CMOS) process.

The invention discloses an LDMOS device with a transverse diffusing buried layer below a grid, comprising a semiconductor body and the grid positioned on the semiconductor body. A first conduction type doping channel region is arranged on the semiconductor body and below the grid; and a first conduction type transverse diffusing buried layer is arranged below the first conduction type doping channel region. The invention can properly reduce the use level of doping ions injected to the first conduction type doping channel region under the precondition of effectively inhibiting the short channel effect of the LDMOS device, thereby reducing the nonlinear capacitors of the LDMOS device so that the radio frequency power and the performance of the LDMOS device are further improved.

A sample and hold amplifier includes an input node for receiving an input current signal, a non-linear sampling capacitor circuit having an input coupled to the input node, an operational amplifier having a negative input coupled to an output of the non-linear sampling capacitor circuit, a positive input coupled to ground, and an output for providing a sample and hold voltage signal, and a linear capacitor coupled between the negative input and the output of the operational amplifier. The non-linear sampling capacitor includes a non-linear capacitor coupled between an intermediate node and ground, a first switch coupled between the input and the intermediate node configured to switch according to a first phase signal, and a second switch coupled between the output and the intermediate node configured to switch according to a second phase signal.

The invention discloses a high-power-factor direct-current current output light-emitting diode (LED) driving circuit with a low-energy-storage capacitor. The LED driving circuit is composed of a diode rectifying bridge (1), an active non-linear capacitor network (3) and a follow-up switch power converter (2). The output end of the diode rectifying bridge (1) supplies power to the active non-linear capacitor network (3). Output voltage of the active non-linear capacitor network (3) is formed by overlapping direct current voltage with alternating current voltage with twice of electric supply frequency. The output voltage of the active non-linear capacitor network (3) supplies power to the follow-up switch power converter (2). The active non-linear capacitor network (3) is composed of a lower-energy-storage capacitor and an active switch network. By means of the LED driving circuit, the low-capacitance capacitor (such as a thin film capacitor and a ceramic medium capacitor) can be utilized to finish the energy storage function.

A variable capacitance circuit includes a first and a second capacitor. A switch having an associated first nonlinear capacitance, selectively couples the first and second capacitors. To compensate for the first nonlinear capacitance, a second nonlinear capacitance is coupled to the switch that has a capacitance value responsive to a change in voltage that moves in a direction of change opposite to a direction of change of the first nonlinear capacitance.

The invention provides a GaN technological parameter statistical analysis method based on large signal equivalent circuit model. The analysis method comprises the following steps: a step 1: establishing a GaN device small signal equivalent circuit model, and extracting small signal model parameters; a step 2: establishing a GaN device large signal equivalent circuit model, and extracting large signal model parameters, that is non-linear current source model parameter and non-linear capacitance model parameter; a step 3: actually measured microwave characteristics of the device are used as objects in order to tune and optimize large signal model parameters; a step 4: extracting multiple-batch GaN device technological parameters based on established large signal model, and carrying out statistical analysis of the technological parameters. The GaN device model technological parameter statistical analysis method firstly establishes the GaN device small signal equivalent circuit model, andthen establishes GaN device large signal equivalent circuit model related to technological parameters, finally technological parameter statistical distribution is obtained by multiple-bath device modeling, and the method is good for device yield analysis and technological parameter optimization.

The invention belongs to the technical field of electronics, and relates to alternating current and direct current conversion and power control, in particular to a high-power factor active valley-fill type alternating current and direct current converter. The high-power factor active valley-fill type alternating current and direct current converter is composed of a diode rectifier bridge (1), an active nonlinear capacitance network (2) and a subsequent switch power converter (3), wherein the output of the diode rectifier bridge (1) supplies the active nonlinear capacitance network (2) and the subsequent switch power converter (3) with power; the output of the active nonlinear capacitance network (2) is controlled to supply the subsequent switch power converter (3) with power.

A first MOS-on-NWELL device is formed on a substrate and has its pickup terminals optionally connected together. A second MOS-on-NWELL device is formed on the substrate and has its pickup terminals optionally connected together. A gate of the first MOS-on-NWELL device is connected to the pickup terminals of the second MOS-on-NWELL device. A gate of the second MOS-on-NWELL device is connected to the pickup terminals of the first MOS-on-NWELL device. A first PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A second PMOS transistor is formed on a substrate and has its source and drain terminals connected together. A gate of the first PMOS transistor is connected to the source and drain terminals of the second PMOS transistor. A gate of the second PMOS transistor is connected to the source and drain terminals of the first PMOS transistor. A combination of the first and second PMOS transistors are connected in parallel with the first and second MOS-on-NWELL devices.

The invention belongs to the integrated circuit design technical field which relates to an integrated circuit design which applies a ferroelectric condenser, in particular to a ferroelectric condenser behavioral model which is applied in an SPICE circuit simulation program. The model utilizes the expression function in the SPICE program to establish a master copy of a non-linear condenser, and the master copy of the non-linear condenser is matched with a differential circuit to be a control circuit and simulates physical behaviors of the ferroelectric condenser. The model comprises a linear condenser, the non-linear condenser, a voltage control voltage source and the differential circuit, wherein, a parallel circuit which consists of the linear condenser and the non-linear condenser is connected in series with the voltage control voltage source and the differential circuit in turn. Compared with the prior art, electric behaviors of the ferroelectric condenser in the model are completely represented by the non-linear condenser and can be precisely evaluated by utilization of an expression. The operation control of the model is completely completed by the differential circuit and the control process is simple, thereby being favorable for improving the simulation speed. Moreover, control signals are differential of input voltage to time, thereby the model is more suitable for simulation of transient states.

An integrated circuit clock analysis system receives a cell library of gates of the integrated circuit and generates a macro model for each of the gates, where each macro model includes at least one of a nonlinear current source model, an input parasitics model or a nonlinear capacitors model. The system then tunes the macro models and generates a simulation deck from an electrical netlist of a layout of the integrated circuit and the tuned macro models. The system then performs clock analysis simulation based on the simulation deck.

The embodiment of the invention includes a method for building an analytical model of a semiconductor device based on the empirical formula of nonlinear capacitance and the empirical formula of a current source. The method includes the following steps of measuring a group of scattering parameters of the semiconductor device under combinations of different environment temperatures and different static biases; determining a group of external parasitic parameters; building a small-signal equivalent circuit model of the semiconductor device; based on the determined external parasitic parameters, removing the external parasitic parameters in the scattering parameters to obtain a group of intrinsic parameters of the small-signal equivalent circuit model of the semiconductor device; using the empirical formula of the nonlinear capacitance to build a nonlinear capacitance model; using the empirical formula of the current source to build a current source model; using the intrinsic parameters, the nonlinear capacitance model and the current source model to build a large-signal equivalent model of the semiconductor device.

Provided is a circuit for compensating nonlinear capacitance to reduce harmonic distortion to the greatest extent. The circuit can improve stray capacitance between transistors and is independent of the adopted process technology. In a preferential instance, a pair of diodes with inversely proportional actions is provided for a parasitic diode in an integrated circuit during operation, so stray capacitance of the transistors in the circuit is linearized. If the diodes do not exist in the circuit, different input signals can give rise to changes of the stray capacitance, and therefore harmonic distortion of the circuit is caused. Another embodiment of the invention further provides a complementary transistor. The complementary transistor forms another stray capacitance which is basically opposite to the stray capacitance in the transistors. In addition, according to proportions of different elements, the two methods can be combined, for instance, the diodes can be added while the complementary transistor is used.