68 results about "Programmable load" patented technology

Adaptive regulated power supply voltages are applied to programmable logic integrated circuits. Control circuitry in a programmable logic IC generates control signals that are transmitted to an external voltage regulator. The voltage regulator generates one or more power supply voltages in response to the control signals. The values of control signals determine the target values of the supply voltages. The control circuitry can adapt the power supply voltages to compensate for temperature and process variations on the IC. The power supply voltages can be programmed by a manufacturer or by a user to achieve desired target values. The control circuitry can also put a programmable logic IC into a sleep mode by dropping the high supply voltage to a low value to reduce power consumption during periods of low usage.

A magnetic stripe data transmission (MST) driver and a method for driving the MST are disclosed. The MST driver is configured to transmit magnetic strip data comprising of streams of pulses. The MST driver comprises a pair of high side switches and a pair of low side switches. The pair of high side switches comprises a first switch and a second switch. The pair of low side switches comprises a third switch and a fourth switch. The first, second, third and fourth switches are arranged in a full bridge type configuration connected across a voltage source and a ground. An inductive coil is connected across outputs of the full bridge type configuration of the switches. The MST driver includes a switch driver configured to drive the pair of low side switches and the pair of high side switches under current slope control using pulse width modulation. The driven load current has a rising portion and a falling portion through the inductive coil in a forward direction or in a reverse direction with programmable load current rising and falling slopes to induce a recognizable back electromagnetic force at a receiver emulating the magnetic strip data during the load current rising and falling portions and to reduce power loss during time periods without signal transmission.

A continuous time linear equalizer comprises an input of a first equalizer path configured to receive a first differential input signal; an input of a second equalizer path configured to receive a second differential input signal; a first programmable load capacitor coupled to an output of the first equalizer path; a second programmable load capacitor coupled to an output of the second equalizer path; and a programmable source capacitor coupled between the first equalizer path and the second equalizer path.

A load transient compensator and method of operating the load transient compensator for reducing the transient response time to a load capable of operating at either of several consumption levels when the load changes its power consumption level . The load transient compensator has a comparator having an output connected to an input of an upper driver and of a lower driver with the output of each of the driver being connected to a gate of a power transistor. When the load is in sleep mode and is about to start being accessed, the upper driver is turned on to turn on its associated transistor to supply additional current to the load, regulated by the comparison circuit. When the load is in the power up mode and it is about to stop being accessed, the lower driver is turned on to turn on its associated transistor to drain current supplied to the load by a supply, regulated by the comparison circuit. This allows a quicker response to the large changes in current required by the load when the load is changing its level of power consumption without greatly increasing the cost of the system containing the load and without compromising the stability of the system.

In a multiprocessor system of a hierarchy configuration as a parallel computer of a common-bus structure, a processing unit (120) in an intermediate stage has a processor (123) having a programmable function that is equal to a normal processor, an instruction memory (125), and a data memory (127). The processing unit (120) receives a status signal from a lower processor (143), and a DMA controller (151) having a memory for the transfer of large sized data performs compression, decompression, programmable load dispersion, and load dispersion according to the state of operation of each lower processor.

In one embodiment, the present invention includes methods and apparatus for providing initial control values to programmable load capacitors of an oscillator, such as that of a real time clock circuit. Using the initial values, the real time clock circuit may begin operation, enabling additional circuitry within an integrated circuit to begin operation. This additional circuitry may cause operating values to program the load capacitors to provide a desired reference clock based on a given system's requirements.

Automated motor vehicle battery voltage protection is provided by setting voltage trip points for increasing engine speed and for shedding selected electrical loads. The system is effected by programming a vehicle body computer which communicates with, and exerts control over, various vehicle system controllers over one or more controller area networks. The body computer is programmed to monitor battery voltage and initiates an increase in engine speed first, and if that fails to restore a minimum battery voltage level, begins shedding loads in a predetermined order.

The invention relates to a super capacitor-based aging state estimation detection system and method. The super capacitor-based aging state estimation detection system includes a programmable power source, a tested super capacitor, a programmable load, a data storage unit, a data acquisition communication unit, a data operating processing unit and an aging state estimation unit. The detection method includes the following steps that: a required condition is set, and test data are acquired and are subjected to frequency division and noise reduction pre-processing; model parameters are identified according to the model of the super capacitor, and characteristic parameters are calculated; and then, aging state evaluation is performed. Compared with the prior art, the super capacitor-based aging state estimation detection system and method of the invention can detect the aging state of the super capacitor in different stages, and has the advantages of high application universality, high condition targeted performance, accurate aging state judgment, short consumed time of aging detection, high reliability of results and the like.

The invention provides a battery stimulation device comprising an AC-DC conversion unit, an adjustable type DC conversion unit, a programmable load, and a control and communication unit. The control and communication unit is electrically connected with a pulse width nodulation input end of a controller of the adjustable type DC conversion unit, and is connected with an external computer by a computer communication interface. Therefore when a user selects the corresponding battery charging and discharging stimulation modes according to the rechargeable battery of the power supplier of the machine to be detected, the control and communication unit is automatically used to control the adjustable-type AC-DC conversion unit and the programmable load mode battery charging and discharging states, then the external power can carry out the machine detection program. In addition, the power of the DC conversion unit is provided by the AC-DC conversion unit, therefore no other battery used for the power supply is required, and the integral structure can be effectively reduced.

A mechanism is provided to address a structure under test and to identify a point of failure. A test open line carries a signal that indicates whether a structure under test is open or closed. A test short line carries a signal that indicates whether a structure under test is shorted. A test structure may include an array of cells, where each cell includes a circuit including structures to test. The cells may be scanned using scan only latches and signals on the test open and/or test short lines may be recorded. A test circuit may include a digital mode and an analog mode. The digital mode provides an open or closed value. The analog mode includes a programmable load. The output of the analog mode provides a resistance value that is relative to the programmable load.

Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

The invention, which belongs to the technical field of the voltage support of the power grid, provides a voltage support experiment testing platform and method with a super-capacitor-based dynamic voltage restorer. In order to solve a problem of lack of accurate theoretical data of the super-capacitor-based dynamic voltage restorer in practical application, the testing platform comprises a programmable grid fault simulator, a programmable load and, and a super-capacitor-based dynamic voltage restorer. The programmable grid fault simulator is used for simulating a voltage drop of a simulated grid and inputting a working voltage for a programmable load; the super-capacitor-based dynamic voltage restorer is used for collecting the voltage outputted by the programmable grid fault simulator, determining a drop situation according to the voltage, and carrying out compensation on the working voltage of the programmable load based on the drop; and the programmable load is used for setting loads with different low-voltage protection threshold values. According to the invention, the provided testing platform is used for providing data for scientific researches. And according to the testing method, the testing platform is realized by using software programs to carry out a simulated experiment.

The invention discloses a field tester for a DC charging pile. The charging gun includes a charging gun input interface and a charging gun output interface, the charging gun input interface is externally connected to the output interface of the charging pile to be verified, and the charging gun output interface is externally connected to the input interface of the charging pile to be verified through a program-controlled load box . The ARM main control module is provided with a BMS simulation unit, the BMS simulation unit is electrically connected to a battery simulator, and the BMS simulation unit is used to generate and output a BMS simulation parameter signal, and the battery simulator obtains the above-mentioned BMS simulation parameter signal and Generate and output simulated test electric energy pulses according to the above BMS simulated parameter signals. The field tester for DC charging piles of the present invention can simulate the whole process of charging such as the BSM protocol and internal resistance changes of electric vehicles, monitor the charging state and calculate the output of electric energy, and realize the measurement and verification of the DC charging piles.

An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a random access memory, programmed via a Joint Test Action Group interface with the plurality of specified load instructions corresponding to the out-of-order processor which, upon initialization, accesses the random access memory to determine said plurality of specified load instructions.

The invention discloses a variable load detection method in electricity meter channeling detection. The method comprises the following steps of: step 1, downloading a detection task by virtue of a detection host, and checking whether user electricity meter numbers needing to be detected are consistent with task requirements; step 2, mounting a photoelectric metering pulse reading device of the detection host on a user electricity meter with channeling suspicion; step 3, connecting the detection slave to a socket on the user side, allowing the detection slave to start working, and changing the load of the socket according to programmable load equipment; and step 4, detecting photoelectric metering pulse generated by different electricity meters by the detection host, and comparing the detection result of the detection host and load change of variable load equipment on the user side. Therefore, the technical effects of improving the electricity meter channeling detection efficiency and electricity meter channeling judgment accuracy and alleviating the labor intensity are achieved.

The invention discloses a radiation effect measurement and control system of a DC-DC (Direct Current-Direct Current) power module. In the system, a synchronizing signal receiving and transmitting unit is connected between a radiation unit and a multi-channel acquisition and storage control unit; a working state simulation unit comprises a programmable power module and a programmable load module; the multi-channel acquisition and storage control unit is connected with a control port of the programmable power module and a control port of the programmable load module; the DC-DC power module is placed in a test region of the radiation unit; an input end of the DC-DC power module is connected with the programmable power module, and an output end of the DC-DC power module is connected with the programmable load module; each data acquisition port of the multi-channel acquisition and storage control unit is connected with input and output ports needing to be monitored of the DC-DC power module. According to the system, high-speed parallel acquisition and storage of a plurality of parameters can be realized, transient pulse can also be completely captured, and switch access testing of a plurality of DC-DC power modules is realized.