35 results about "All-pass filter" patented technology

Automated communication channel selection is provided. A method, system, and computer readable storage device automatically perform a discovery process of a MoCA® network, to determine a topology of the network, perform a spectrum analysis of a DOCSIS® network of which a portion of the frequency range may be shared, apply one or more business rules to the collected network and spectrum usage data, and determine an optimized channel configuration for transmitting data to end devices in a local network. For example, the channel configuration may be configured for optimal bandwidth allocation, transmission speeds, signal quality, etc., without interferences within the shared frequency spectrum range. A gateway device may include a filter that can be reconfigured as an all-pass filter or as a variable low-pass filter based on the channel configuration determination. The MoCA® network may be reconfigured to operate within a defined frequency range based on the determined channel configuration.

The application discloses a loudspeaker phase equalization signal processing system and a pole parameter determination method thereof, which equalizes the loudspeaker phase response in a set equalization frequency range to linear phase, and the system comprises a phase controller and a group delay equalizer in cascade; the phase controller is a first-order IIR all-pass filter; the group delay equalizer comprises S low-order IIR all-pass filters in cascade, wherein the first N1 low-order IIR all-pass filters are low-order causal IIR all-pass filters, and the last N2 low-order IIR all-pass filters are low-order non-causal IIR all-pass filters. The application can equalize the loudspeaker phase through the all-pass filter with low operation complexity and parameters, can significantly reduce the calculation amount required by low-frequency phase equalization, can improve the linear degree of the loudspeaker phase response, and can improve the sound quality and listening experience.

Techniques are disclosed for self-interference signal cancellation. A self-interference cancellation method includes measuring an error between an output of a hardware cancellation circuit and an output of a software model of the hardware cancellation circuit. The method further includes estimating an amplitude error, a phase error, and a delay error based on the measured error and the output of the hardware cancellation circuit, and locating a largest frequency domain error peak in the measured error. The method further includes applying an all-pass filter to the estimated and measured signals at the peak error frequency to produce a filtered estimated signal and a filtered measured signal and optimizing the filtered estimated signal and the filtered measured signal to obtain an optimized canceller setting. The optimized canceller setting is provided to the hardware cancellation circuit.

The application discloses a frequency divider and a frequency division system, and relates to the field of signal processing.The frequency divider comprises an input port, an all-pass filter, a first adder and a second adder.The input port is connected with the input end of the all-pass filter, the input end of the first adder and the input end of the second adder.The output end of the all-pass filter is connected with the input end of the first adder and the input end of the second adder.The all-pass filter filters an original signal input by the input port based on preset filter coefficients to obtain a filtered first signal.The output end of the first adder is connected with a high-pass output port of the frequency divider, and the output end of the second adder is connected with a low-pass output port of the frequency divider.The first adder is used for adding a negative value of the first signal to the original signal to obtain a high-pass signal of the frequency divider.The second adder is used for adding the first signal to the original signal to obtain a low-pass signal of the frequency divider.The application provides a frequency divider based on an all-pass filter, which effectively reduces the occupied computing resources of the frequency divider.

The invention relates to the technical field of three-phase systems, and provides a three-phase voltage state estimation method and system based on virtual coordinates, and the method comprises the steps: calculating the voltage peak value of each phase for three-phase voltages, and determining that a phase is open if the peak voltage of a certain phase is lower than a threshold value in the three peak voltages; for three-phase voltage, virtual beta-axis voltage is generated through an all-pass filter, actual beta-axis voltage is obtained through Clark transformation, the product of the virtual beta-axis voltage and the actual beta-axis voltage serves as an evaluation function, and a positive sequence and a negative sequence are distinguished according to the positive and negative of the evaluation function. The system state can be accurately and effectively judged under the conditions of three-phase imbalance and voltage distortion, the anti-noise capability and the anti-harmonic interference capability are high, and safe and stable operation of equipment under the abnormal condition is ensured.

The application discloses a sound source orientation method and device based on an all-pass filter, equipment and a medium, and relates to the technical field of computers. The method comprises the following steps: recording a sound source based on a linear microphone array to obtain multi-channel recording data, performing first generalized cross-correlation operation on a wideband excitation signal and the multi-channel recording data, performing slicing and second generalized cross-correlation operation on the obtained first cross-correlation result, determining an initial delay value by using a quadratic function fitting method, and judging whether the absolute value of the initial delay value is greater than a preset threshold. If yes, the multi-channel sliced data is up-sampled, the signal delay relationship of each adjacent channel is modeled by using a Thiran all-pass filter, the target delay value of each adjacent channel is determined based on the obtained linear equation and by using a least square method, and the sound source incidence angle is determined by using the target parameters of the linear microphone array. The method breaks through the constraint of the Rayleigh limit and performs high-precision delay estimation, so that the accuracy of sound source orientation is ensured.

The application discloses a low-power consumption full-differential multiple harmonic IQ zero intermediate frequency mixing circuit, which comprises a quadrature all-pass filter QAF, a phase-shifting driver based on current vector synthesis, an mth harmonic frequency mixer I_MIXER based on a frequency multiplication structure and an mth harmonic frequency mixer Q_MIXER based on a frequency multiplication structure. The input local oscillator differential signal is changed into a quadrature IQ differential signal through the quadrature all-pass filter, then the driver module is used to realize the amplification signal and phase-shifting functions, generate and amplify the differential signal with the required phase, and then the differential signal is injected into the IQ mixer, and the mixer is used to realize the frequency multiplication function through the circuit structure based on the frequency multiplier and the state class B bias state of the adjusting transistor, so that the local oscillator signal is multiplied and mixed with the input RF signal. The application saves the power consumption of the frequency multiplier, effectively reduces the power consumption of the local oscillator signal link, and optimizes the linearity and noise of the mixer.

The invention provides an FI-DAC system nonlinear phase error calibration method based on GA-Dogleg-BFGS, belongs to the technical field of FI-DAC system phase error calibration, and aims to solve the problems that the existing multichannel FI-DAC system phase error calibration is difficult to adapt to multi-band synchronous correction of broadband signals and lacks flexible expansion capability, and the method comprises the following steps: S1, adding a multi-tone test signal in an FPGA, phase unwrapping processing is carried out on the collected phase data; s2, performing nonlinear phase correction on the second-order section cascade type all-pass filter, and calculating a phase correction error; s3, constructing a weighted nonlinear minimum mean square problem; s4, the weighted nonlinear minimum mean square problem is solved in a staged mode based on a GA-dog-BFGS algorithm; and S5, according to the solving result, the coefficient of the digital all-pass filter is re-issued to each sub-DAC channel for verification.

An electronic device may include a microphone that receives a first acoustic sound and generates a first audio signal based on the first acoustic sound. The electronic device may also include filter circuitry having multiple filter stages, each filter stage including an all-pass filter and a multiplier where respective outputs of each of the filter stages are summed in series. Moreover, the filter circuitry may determine a filter input based on the first audio signal and process the filter input via the filter stages to generate a second audio signal. The electronic device may also include a speaker to output a second acoustic sound based on the second audio signal.

An apparatus is provided according to an embodiment for processing a first audio signal to generate two or more second audio signals. The apparatus includes a decorrelation module (110) configured to generate two or more processed signals from the first audio signal. The decorrelation module (110) is configured to generate each of the two or more processed signals by transforming the first audio signal to the frequency domain to obtain a transformed audio signal, by applying a delay, by applying a full-pass filter to the transformed audio signal, by performing envelope shaping, and by performing an inverse transform to obtain the processed signal. Furthermore, the apparatus includes a mixer (120) configured to generate each of the two or more second audio signals by mixing at least two of the two or more processed signals. The decorrelation module (110) is configured to apply the full-pass filter using different filter coefficients to generate each of the two or more processed signals. The mixer (120) is configured to mix in different ways to generate each of the two or more second audio signals.

An electronic device may include a microphone that receives a first acoustic sound and generates a first audio signal based on the first acoustic sound. The electronic device may also include filter circuitry having multiple filter stages, each filter stage including an all-pass filter and a multiplier where respective outputs of each of the filter stages are summed in series. Moreover, the filter circuitry may determine a filter input based on the first audio signal and process the filter input via the filter stages to generate a second audio signal. The electronic device may also include a speaker to output a second acoustic sound based on the second audio signal.

A Coriolis flow meter includes a sensor system generating a first sensor signal and a second sensor signal. A measuring or operating circuit includes a microprocessor designed to operate an excitation system. An all-pass filter having a filter coefficient and which is designed to receive the first sensor signal and to generate a filtered first sensor signal is provided. The measuring or operating circuit receives the filtered first sensor signal and the second sensor signal, and has a control circuit designed to control the filter coefficient, based on the filtered first sensor signal and the second sensor signal, or based on a variable derived from the filtered first sensor signal and the second sensor signal, such that a control criterion is satisfied, and a first measurement value representing the process variable from the filter coefficient is generated.

The invention belongs to the technical field of digital signal processing in a radio frequency / microwave communication system, and particularly discloses a multi-frequency parallel compensation method for a nonlinear phase of a radio frequency device, which is characterized by comprising the following steps of: S1, acquiring a phase-frequency curve p (f) of an output signal of a radio frequency end of the radio frequency device; s2, converting the phase frequency curve p (f) into a plurality of amplitude-frequency responses amp (f), performing inverse Fourier transform on the amp (f) to generate a filter coefficient hp, and performing M-order truncation and N-bit fixed-point quantization on the hp to generate an all-pass filter coefficient hp (m); s3, performing orthogonal down-conversion on a digital intermediate frequency signal y (n) to be compensated to a baseband, inputting the digital intermediate frequency signal y (n) into the all-pass filter, and simultaneously completing phase compensation on all frequency components contained in the y (n) by utilizing a group delay characteristic; and the compensated baseband signal is recovered to the original intermediate frequency through quadrature up-conversion, and an output signal with a corrected nonlinear phase is obtained. Phase modulation can be carried out on multiple frequency signals at the same time, frequency measurement is not needed, and frequency and data alignment does not need to be considered.

The utility model relates to the technical field of all-pass filter processors, in particular to an FIR (Finite Impulse Response) digital all-pass filter processor, which comprises a case, an aluminum panel arranged on the case, a cover arranged on the case, a circuit board arranged on the case, sliding rails symmetrically arranged in the case, insertion rods symmetrically arranged on the aluminum panel, and an elastic piece arranged on the insertion rods. The sliding rail is fixedly connected with the inner wall of the machine box, the sliding rail is in a strip shape, sliding grooves are symmetrically formed in the sliding rail, the sliding grooves are in a penetrating shape, a fan is arranged in the machine box, a power panel is arranged in the machine box, an input panel is arranged in the machine box, the input panel is matched with the aluminum panel, and the fan is matched with the aluminum panel. Through the arrangement of the sliding grooves and the insertion rods, the disassembly smoothness can be improved when the aluminum panel needs to be disassembled, abrasion caused by mutual collision of the buckles and the clamping grooves during buckle splicing disassembly is avoided, compared with the prior art, the disassembly smoothness of the aluminum panel can be effectively improved, and then the disassembly and replacement efficiency of the case is improved.

A musical tone signal generation apparatus, method, and storage medium that utilizes an all-pass filter for efficient processing. The method involves setting a first delay unit that generates a delay corresponding to a specified pitch, setting its pre-stage delay unit as a 0th delay unit, and its post-stage delay unit as a 2nd delay unit. At least three fractional delay blocks are connected to the first, 0th, and 2nd delay units, respectively. In a scenario where, based on a change in the specified pitch, one of the 0th and 2nd delay units is set as a new first delay unit, and the pre-stage delay unit of the new first delay unit is set as a new 0th delay unit, and the post-stage delay unit of the new first delay unit is set as a new 2nd delay unit, one of the 0th and 2nd delay units continues to be connected to the fractional delay blocks, and at least one of the new 0th and new 2nd delay units is then changed to be connected to at least one of the fractional delay blocks other than the fractional delay block connected to the new first delay unit.

Systems, devices, and methods are described for determining an adapted pair of "coupled" left / right ear head related transfer functions (HRTFs) from a pair of original left / right ear head related transfer functions (HRTFs), where the inter-ear delay of the coupled HRTFs is formed using an all-pass filter that provides the correct inter-ear delay at low frequencies. The all-pass filter is adapted to limit inter-ear phase differences at high frequencies. In addition, a low complexity process for rapidly generating a suitable all-pass filter is described.

Simulated audio signals in a virtual environment are decorrelated by obtaining (102) a first set of decorrelation filters (eg. frequency-selective phase shifting all-pass filters as in Fig. 3), evalua

The present disclosure relates to an analog neuron with S-domain properties. An analog element is described for use as a neuron in a recurrent neural network, the analog element having storage of previous layer states and being a continuous-time circuit without discrete clocking intervals. The element is characterized and described by the Laplace s-domain operator, as opposed to digital solutions using the z-domain operator which is suited for quantized time description. Instead of using an all-pass filter, the analog equivalent of a unit delay in the z-domain, a finite-gain integrator can be used to provide delay in the analog s-domain as a simpler circuit. The resulting circuit can be easily implemented at the transistor level.

The invention provides a dual-channel time-interleaved ADC mismatch correction method and system, and a storage medium. The method comprises the following steps: S1, splitting an output signal of a dual-channel time-interleaved ADC into two independent channel signal sequences; s2, determining a unified direct current value based on the deviation between the average value of each channel signal sequence and the ADC quantization coding center value; s3, respectively calculating signal amplitude values of the two channels to determine a gain ratio, and correcting mismatching of the gains of the two channels according to the gain ratio; s4, converting the error between the actual phase difference of the two channels and the ideal phase difference into Delta sampling periods so as to establish an all-pass filter to perform time sequence correction on a non-reference channel; and S5, combining the corrected signal sequences of the two channels, and superposing a unified direct current value. Therefore, the problem that spurious interference occurs in an output spectrum due to mismatching of imbalance, mismatching of gain and mismatching of time sequence of the dual-channel time-interleaved ADC is solved.

The invention provides an FI-DAC system phase frequency error correction method based on BO-Adabound, belongs to the technical field of phase frequency error calibration, and aims at solving the problems that a traditional nonlinear phase frequency error correction method is poor in performance of phase frequency characteristics of sub-band target frequency and low in correction precision, and the method comprises the steps that an initial target function is calculated according to an input signal; calculating an initial objective function output based on an AdaBound algorithm; performing Bayesian loop optimization on the initial data set to obtain a new evaluation point of an integral adjustment factor; obtaining a new integral adjustment factor based on the new evaluation point of the integral adjustment factor, and obtaining an Adabound initial parameter through a table look-up method; carrying out Adabound training, updating solving parameters, iteratively updating target functions corresponding to the parameters, and obtaining current optimal filter parameters and the target functions; and updating the data set based on the optimal objective function and carrying out Bayesian loop optimization again until a global convergence condition is met or the maximum number of iterations is reached, and outputting an optimal all-pass filter parameter.

This invention discloses an APF control method with frequency adaptation under grid voltage imbalance. The inner loop (voltage loop) uses PI control to stabilize the DC bus voltage, achieving stable energy exchange between the two sides of the converter. The outer loop (current loop) employs a composite control algorithm combining proportional-integral (PI), proportional-complex-integral (PCI), and proportional-resonant (PR) control to achieve precise control of the compensation current. When the grid voltage is balanced, only PI plus PCI control is used, resulting in a large stability margin and fast dynamic response. When the grid voltage is unbalanced, a full-pass filter separates the reference signal into positive and negative sequences. The positive sequence component still uses PI plus PCI control, while the negative sequence component uses PI plus PR control, addressing the poor stability of single PCI control under grid voltage imbalance. A frequency-locked loop is introduced into the system to track and control the grid frequency in real time, improving current control accuracy and simplifying the computational complexity of the control algorithm. This method is applicable to other three-phase inverter control systems.

The invention provides a positive and negative sequence electric quantity separation method and device. The method comprises the steps of obtaining an instantaneous electric quantity signal in a three-phase power grid; performing phase angle deviation of a preset angle on the instantaneous electric quantity signal based on an all-pass filter to obtain an instantaneous orthogonal electric quantity signal; and determining a positive sequence component and a negative sequence component of the instantaneous electric quantity signal according to the instantaneous electric quantity signal and the instantaneous orthogonal electric quantity signal. The phase angle deviation of the preset angle is performed on the instantaneous electric quantity signal based on the all-pass filter so as to acquire the instantaneous orthogonal electric quantity signal, and the phase angle deviation can be realized with extremely high precision by utilizing the characteristic that the all-pass filter keeps the amplitude response constant in the whole frequency range and only changes the phase of the signal, so that the error caused by the amplitude change is avoided. According to the method, the instantaneous orthogonal electric quantity signal is obtained firstly, then the positive sequence component and the negative sequence component are determined in combination with the instantaneous electric quantity signal, the positive sequence component and the negative sequence component are rapidly obtained in a three-phase power grid system with the high real-time performance requirement by means of the orthogonal relation between the signals, and error analysis is facilitated.

The invention discloses a frequency divider and a frequency division type system, and relates to the field of signal processing. The frequency divider comprises an input port which is connected with the input end of an all-pass filter, the input end of a first summator and the input end of a second summator; the output end of the all-pass filter is connected with the input end of the first adder and the input end of the second adder, and the all-pass filter filters the original signal input by the input port based on a preset filter coefficient so as to obtain a filtered first signal; the output end of the first adder is connected with a high-pass output port of the frequency divider, and the output end of the second adder is connected with a low-pass output port of the frequency divider; the first adder is used for adding the negative value of the first signal and the original signal to obtain a high-pass signal of the frequency divider; the second adder is configured to add the first signal to the original signal to obtain a low pass signal of the frequency divider. The invention provides a frequency divider based on an all-pass filter. Computing resources occupied by the frequency divider are effectively reduced.

The embodiment of the invention provides a signal separation system, method and device, a storage medium and a program product, and relates to the technical field of signal processing. The system comprises a feature extraction module used for obtaining an AC voltage signal having the same frequency as a hybrid signal fundamental frequency, converting the AC voltage signal into a DC reference voltage, and amplifying the DC reference voltage based on a target frequency to obtain a feature delay voltage corresponding to the target frequency; the physical field regulation and control module is used for acquiring the characteristic delay voltage and driving a voltage-controlled element to generate a physical field with continuously changing intensity through the characteristic delay voltage, so that passive element parameters of the first-order all-pass filter continuously change along with the intensity of the physical field to generate a delay signal matched with a target frequency; and the signal separation and recovery module is used for separating a target frequency component from the mixed signal according to the delay signal. The system is used for achieving the effect of continuously and flexibly realizing signal separation of different target frequencies.

A capacitance sensing assembly is provided. The capacitance sensing assembly includes an op-amp arranged with four complex impedance circuits and a sensing capacitor connected to the fourth complex impedance circuit and ground; or to the non-inverting input of the op-amp, the fourth complex impedance circuit, ground and the second terminal of the fourth complex impedance circuit, wherein the fourth complex impedance circuit is connected in parallel to the sensing capacitor. The complex impedance circuits are configured to increase a gradient of a phase to frequency response curve of the capacitance sensing assembly relative to that of an all-pass filter with a second electrode of a capacitor connected to the non-inverting input of the op-amp and the ground without the fourth complex impedance circuit.

Systems, devices, and methods are described for determining a "coupled" pair of left / right ear HRTFs adapted from the original pair of left / right ear HRTFs. The interaural delay of the coupled HRTF is formed using a whole-pass filter that provides the correct interaural delay at low frequencies. The whole-pass filter is adapted to limit the interaural phase difference at high frequencies. Furthermore, a low-complexity process for the rapid generation of a suitable whole-pass filter is described.

A system includes one or more computing devices that encode spatial perceptual cues into a monaural channel to generate a plurality of output channels. A computing device determines a target amplitude response for the mid and side channels of the plurality of output channels, defining a spatial perceptual associated with one or more frequency-dependent phase shifts. The computing device determines a transfer function of a single-input, multi-output allpass filter based on the target amplitude response and determines coefficients of the allpass filter based on the transfer function, and processes the monaural channel with the coefficients of the allpass filter to generate the plurality of channels having the encoded spatial perceptual cues. The allpass filter is configured to be colorless with respect to the individual output channels, allowing for the placement of spatial cues into the audio stream to be decoupled from the overall coloration of the audio.

The invention discloses a two-phase code baseband signal signal-to-noise ratio improvement method based on signal amplitude enhancement, and mainly solves the problems that the bit error rate of baseband signal extraction is increased and the pulse compression performance is affected due to the fact that the signal amplitude is low when the signal-to-noise ratio is lower than 0dB in the prior art. The method comprises the following steps: carrying out orthogonal mixing by adopting an orthogonal all-pass filter to generate I-path and Q-path signals, and carrying out four-path parallel operation on the I-path and Q-path signals to obtain four intermediate signals; squaring, subtraction and sign bit taking are carried out on the Q-path signal and the I-path signal, a frequency-doubled signal of frequency offset is generated, and sine and cosine signals of the frequency offset are obtained through frequency halving; and performing table look-up mapping on the three frequency offset signals and the four intermediate signals to obtain a baseband signal to complete pulse compression. The signal processing paths of the key nodes are optimized, the signal amplitude of 15 key nodes is enhanced without increasing noise, the signal amplitude can be enhanced by more than two times, the signal-to-noise ratio is improved by more than 6dB, the bit error rate is reduced, and the method is suitable for scenes with high signal quality requirements, such as radar detection, communication navigation and the like.