32results about How to "Eliminate DC Offset" patented technology

The invention discloses a radio frequency transmitting-receiving device, comprising a duplexer, a radio-frequency front end, a filter, an automatic-grain adjuster, a demodulator, a buffer, an oscillator, a memory, a power amplifier, a baseband processor and a digital controller. The radio frequency transmitting-receiving device can be produced by a widely-used CMOS process, all circuits can be realized in a chip and the system has simple structure; and the whole frequency transmitting-receiving device has low power consumption so as to solve the problem of ultra-low power consumption of a sight glass in a capsule during application and is especially suitable to be applied to communication fields of wireless sensor networks, implantable medical applications and other ultra-low power consumption.

The invention discloses a signal processing apparatus applied to time-varying signals. The signal processing apparatus comprises a summator and a weighting integrator. The summator is used for receiving a first input signal and an integrated signal and generating a first output signal, wherein the first output signal is equal to a result obtained by subjecting the first input signal and the integrated signal to subtraction. The weighting integrator is used for receiving the first output signal and generating the integrated signal and comprises a weighting function generator, a multiplier and an accumulator, wherein the weighting function generator is used for receiving the first output signal and generating a weighting function when the first output signal passes by the position nearby a zero crossing point, the multiplier is used for multiplying the weighting function by the first output signal, and the accumulator is connected with the multiplier and used for accumulating the result obtained by multiplying the weighting function by the first output signal and generating the integrated signal according to the accumulated result. The signal processing apparatus applied to the time-varying signals has the advantage that direct-current offset in a photoelectronic signal can be eliminated.

The invention relates to an amplifier with ultralow direct current (DC) offset at an input end and an analog / digital (A / D) converter. The amplifier with the ultralow DC offset at the input end comprises a chopped wave modulator, a sampling instrument, a correlated double sampling (CDS) instrument and an amplifying / integration unit which are connected in sequence. A chopped wave demodulator is arranged in a circuit behind the sampling instrument. The chopped wave modulator and the chopped wave demodulator are used for eliminating residual DC offset generated due to imperfection of the CDS instrument and the other circuit components. On the other hand, the CDS instrument can also eliminate residual DC offset of the chopped wave modulator and the chopped wave demodulator. Due to the fact that the chopped wave modulator and the chopped wave demodulator modulate the residual DC offset of the CDS instrument and other circuit components at the clock frequency of 2*ck_chop to generate high-frequency modulating signals, input signals and the modulating signals do not overlap in a frequency domain. Consequently, the modulating signals can be eliminated at a low-pass filter which is connected with an output end of the amplifier with the ultralow DC offset at the input end. Therefore, the purpose of eliminating the residual DC offset of sampling signals is achieved.

The invention discloses a complementary metal oxide semiconductor (CMOS) automatic gain control amplifier for canceling direct current offset. The CMOS automatic gain control amplifier comprises a cascade amplification link, an automatic gain control feedback loop and a direct current offset canceling feedback loop. The cascade amplification link uses multistage variable gain amplification units for cascading and can achieve high gain and enlarge high gain dynamic ranges. The automatic gain control feedback loop uses a charge pump structure and has the advantages that the automatic gain control feedback loop is less influenced by process deviation and temperature deviation, is capable of accurately detecting narrow-band and wide-band signal amplitude and is suitable for achieving CMOS processes. The direct current offset canceling feedback loop uses two-stage negative feedback loops, and each of the two-stage negative feedback loops uses an integrator as low-pass negative feedback; an active device is used as an integrator input resistor, and an equivalent resistor is provided with characteristics of temperature compensation; and the automatic gain control amplifier for canceling the direct current offset is capable of effectively canceling the direct current offset superposed by a preceding stage circuit and the direct current offset of the amplification link and is provided with a lower high pass corner frequency and a higher integrated level, and the automatic gain control amplifier for canceling the direct current offset is small in low-frequency signal loss and requires no off-chip passive devices (high value resistors or capacitors and the like). The automatic gain control amplifier is applicable to wireless communication receivers with zero intermediate frequency structures in the CMOS processes.

The invention provides a direct current offset calibration system and method. The system is arranged at a receiver end to process differential input signals and operates in one of a working mode, a first calibration mode and a second calibration mode. The system comprises a matching circuit, an equalization circuit, an amplification circuit, a control circuit, a first digital-to-analog conversion circuit and a second digital-to-analog conversion circuit, wherein the equalization circuit is electrically connected with the matching circuit, the amplification circuit is electrically connected with the equalization circuit, and the control circuit is electrically connected with the amplification circuit. In the operating mode, the matching circuit provides impedance matching for the differential input signal. A first digital signal and a second digital signal are respectively output in the first calibration mode and the second calibration mode. The first digital-to-analog conversion circuit and the second digital-to-analog conversion circuit respectively generate a first differential calibration signal and a second differential calibration signal according to the first digital signal and the second digital signal. In the first calibration mode, the amplification circuit generates a first amplification signal according to the first differential calibration signal, and feeds back and adjusts the first digital signal; and in the second calibration mode, the equalization circuit and the amplification circuit generate a second amplification signal according to the second digital signal, and feed back and adjust the second digital signal.