15 results about "Half-band filter" patented technology

The invention discloses a digital filter structure for sigma-delta ADC downsampling, which adopts an all-digital method to construct a third-order single-ring feed-forward system, and integrates an integral-comb cascade filter, a compensation filter and a half-band filter in series. Wherein the integral-comb cascade filter is of a recursive structure formed by connecting multiple stages of integrators in series, downsampling multiple programming is supported, and the parallelism degree and the hardware utilization rate are improved by advancing the position of a delay unit. The compensation filter adopts odd-order integrator multi-branch parallel, so that the resource occupation is reduced, and the processing speed is remarkably improved; the half-band filter adjusts the coefficient position by using a retiming technology, reduces the delay of a critical path, improves the highest frequency of the system, reduces the calculation amount through a symmetric structure and a multiplexing extraction path, and reduces the operation rate demand and data loss through preposed extraction. According to the invention, low power consumption, low hardware consumption and high design flexibility of the downsampling filter in the sigma-delta ADC digital module are realized.

The invention discloses a high-order digital decimation filter with a variable decimation multiple, which comprises a cascade comb filter used for downsampling and anti-aliasing filtering, filtering high-frequency components and obtaining low-frequency density signals, and a compensation filter connected to the output end of the cascade comb filter and used for compensating passband attenuation and performing double decimation on the signals, and the output end of the compensation filter is connected with a half-band filter for realizing third-stage signal extraction. The invention further discloses a filtering method of the high-order digital decimation filter with the variable decimation multiple. Aiming at the defects that a traditional single-stage FIR filter is high in hardware requirement, complex in design, high in filter order and not easy to implement and the like, and aiming at the defect that a CIC filter is insufficient in passband flatness, a CFIR compensation filter is used for compensation, and finally a half-band filter is used for frequency reduction.

The application discloses a high-speed sampling data real-time extraction method based on parallel digital filters, which comprises the following steps: collecting a measured signal through a collection system of a mixed domain oscilloscope to obtain parallel multi-channel signals; realizing large-multiple real-time extraction filtering through a parallel CIC filter and a cascaded parallel half-band filter to obtain serial data; and finally performing serial extraction on the serial data to obtain output data, so that the frequency resolution of the spectrum analysis function of the oscilloscope can be significantly improved without increasing the FFT length.

The invention discloses a high-speed sampling data real-time extraction method based on a parallel digital filter, and the method comprises the steps: collecting a measured signal through a collection system of a mixed-domain oscilloscope, obtaining a plurality of parallel signals, achieving the high-magnification real-time extraction filtering through a parallel CIC filter and a cascaded parallel half-band filter, obtaining serial data, and carrying out the real-time extraction of the serial data through the parallel CIC filter and the cascaded parallel half-band filter. And finally, performing serial extraction on the serial data to obtain output data, so that the frequency resolution of the spectral analysis function of the oscilloscope can be remarkably improved under the condition that the FFT length is not increased.

The invention discloses a multi-modulation system carrier synchronization integrated judging and locking device for satellite-to-ground data transmission, and belongs to the field of satellite-to-ground data transmission. The device comprises an AD conversion module, a digital down-conversion module, a low-pass filtering module, a half-band filter bank module, a digital resampling module, a matched filtering module, a carrier phase tracking module, a carrier phase error calculation module, a timing error calculation module and a carrier synchronization judging and locking module. According to the invention, the carrier synchronization integrated locking judgment function of multiple modulation systems in a satellite-ground high-speed data transmission CCM transmission mode and a VCM transmission mode is realized, the adaptability of the device is improved, and the device is convenient to realize and popularize.

The invention discloses a digital baseband communication receiving link circuit and a data receiving method, and relates to the technical field of data communication, the circuit comprises a downsampling module, a code element shaping module, a code element synchronization module, a decoding module and a CRC verification module; the down-sampling module comprises a CIC down-sampling circuit and a half-band filter down-sampling circuit; the code element shaping module comprises a delay circuit, a level comparison circuit and a level overturning circuit; the code element synchronization module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling decision circuit; the decoding module comprises a decoding state machine circuit and a data judgment circuit; and the CRC verification module comprises a CRC mode control circuit, a CRC (Cyclic Redundancy Check)-5 verification circuit and a CRC-16 verification circuit. According to the invention, the inter-symbol interference and the bit error rate caused by the synchronization error are reduced, so that the accuracy and the signal-to-noise ratio tolerance of the received data are improved on the whole.

The present invention discloses a half-band filter, which comprises a read-write control module, a filtering calculation module, a data cache space and a filter coefficient memory; the read-write control module is used to control the writing of to-be-filtered data input into the half-band filter into the data cache space, and counts with a value of 2 as the change value of a single count to generate a read address; the read-write control module is used to read the to-be-filtered data from the data cache space using the read address generated by counting according to the relationship between the number of to-be-filtered data written into the data cache space and a transposition enable count threshold, and transmit the read to-be-filtered data to the filtering calculation module in sequence; the filtering calculation module is used to control the to-be-filtered data output by the data cache space and the filter coefficients output by the filter coefficient memory in the same order as that of the data cache space to perform filtering calculation; wherein the difference between the number of taps of the half-band filter and the value 1 is equal to the transposition enable count threshold.

The application discloses a kind of digital filter structures for Σ-ΔADC downsampling, adopt full digital method to construct three-order single loop feedforward system, series integrated integral-comb cascaded filter, compensation filter and half-band filter.Integral-comb cascaded filter is composed of multistage integrator series recursion structure, support downsampling multiple programmable, improve parallelism and hardware utilization by moving delay unit position in advance.Compensation filter adopts odd-order integrator multi-branch parallel, reduce resource occupation, significantly improve processing speed;Half-band filter uses retiming technology to adjust coefficient position, reduce critical path delay, improve the highest frequency of system, while reducing the amount of calculation through symmetric structure and multiplexing extraction path, front extraction reduces the demand of operation rate and data loss.The application realizes low power consumption, low hardware consumption and high design flexibility of downsampling filter in Σ-ΔADC digital module.

Systems and techniques are provided for energy detection by a wireless communication device. A method includes filtering a received signal using a half-band (HB) filter with a configured cut-off frequency to obtain a filtered signal based on the received signal, wherein the HB filter is associated with a receiver of the wireless communication device, and the received signal comprises a wireless transmission received by the receiver. Information indicative of a power level can be determined corresponding to a detected energy associated with the filtered signal. Embodiments of the wireless communication device process the received signal according to the information indicative of the power level, before demodulated symbols become available from a receiver downsampling chain.

The invention discloses a high-speed data transmission demodulation device based on multi-GPU parallel processing, and belongs to the technical field of satellite-ground data transmission. The device comprises a digital down-conversion unit, a low-pass filtering unit, a half-band filter bank unit, a digital resampling unit, a complex filtering unit, a digital AGC unit, a data extraction unit, a carrier Doppler frequency offset estimation unit, a forming coefficient storage unit, a coefficient convolution unit, a coefficient interception unit, a control word scanning unit and a carrier phase error compensation unit. A timing error calculation unit, a carrier phase error calculation unit, an error accumulation unit, and an error weighting unit. The method has the characteristics of high implementation reliability, high stability, low implementation complexity and the like.

The invention discloses a decimation rate configurable digital filter applied to a BMS (Battery Management System). The decimation rate configurable digital filter comprises a decimation filter, a compensation filter, a half-band filter and an SPI (Serial Peripheral Interface) configuration interface circuit, the decimation filter, the compensation filter and the half-band filter are sequentially connected in series, and the SPI configuration interface circuit is respectively connected with clock control ends of the decimation filter, the compensation filter and the half-band filter; the decimation filter is used for performing multiple extraction on the input signal to obtain a density wave; the compensation filter is used for compensating the density wave by adopting amplitude-frequency characteristics opposite to those of the decimation filter to obtain the compensated density wave; the half-band filter is used for carrying out frequency-doubled reduction operation on the compensated density wave to obtain a digital signal; the SPI configuration interface circuit is used for respectively configuring decimation factors of the decimation filter, the compensation filter and the half-band filter according to an input clock input signal SCLK and an externally input control instruction. The method can flexibly adapt to the requirements of different application scenes.

The present invention discloses an FIR filter multiplexing system. The FIR filter multiplexing system comprises a filter type selection module and a filter function realization module. The filter function realization module comprises a read-write control submodule, a filter calculation submodule, a data buffer and a filter coefficient memory. The FIR filter multiplexing system is compatible with both half-band filters and non-half-band filters. The selection module is used to integrate two different types of filters, half-band filters and non-half-band filters, into one system. Therefore, relevant counting parameters can be selected to realize the extraction filtering function of the corresponding type of filter on input data, so that the FIR filter multiplexing system forms a filter system with strong universality.

The invention discloses a parallel interpolation filtering device, and belongs to the field of communication, chips and digital signal processing, the device realizes 2-path, 4-path and 8-path parallel interpolation filtering based on a parallel interpolation filtering module of a half-band filter, and the parallel interpolation filtering module comprises an internal operation unit and a result output unit. The internal arithmetic unit completes interpolation and filtering processing on each piece of input data at the same time, that is, the input data is multiplied by a corresponding non-zero coefficient in half-band filter coefficients, and a multiplied result and a result of a previous register are accumulated and then stored in the current register; and outputting output data which is twice of the input data paths. According to the invention, double interpolation and half-band filtering are subjected to fusion design, so that the processing delay is reduced; only the calculation intermediate result is cached, so that the use of a register is reduced; large combinational logic does not exist between the registers, so that the operation clock of the whole circuit is improved; and the input data does not need to be subjected to serial-parallel conversion again, so that the complexity of control logic is reduced.

The invention discloses a reconfigurable half-band cascade metering method, a chip architecture and a chip, and the metering method comprises the steps: carrying out the improvement of a metering method of an existing CIC architecture, replacing all low-pass filters with half-band filters HBF, and carrying out the metering of an input signal through employing the improved metering method; the chip architecture is used for realizing the recording method and specifically comprises an analog ADC (Analog to Digital Converter), the first processor, a first SPI (Serial Peripheral Interface) module, a first register, a random access memory, a second processor, a second register, a second SPI module and a third register, the chip adopts the chip framework; according to the method, the problem of relatively large metering errors is solved, the method and the architecture are proved to have excellent operation capability and extremely low hardware implementation cost in a power grid frequency fluctuation scene, and meanwhile, the method and the architecture have relatively high reconstruction flexibility to face complex multi-metering application scenes.

The present invention discloses a cascaded half-band filter RTL automatic generation system and method, belonging to the field of digital integrated circuit design, including a cascaded half-band filter design module, a cascaded half-band filter RTL generation module, and a cascaded half-band filter test platform generation module; the cascaded half-band filter design module designs a cascaded half-band filter based on Matlab according to user requirement parameters, and transfers the design parameters to the cascaded half-band filter RTL generation module; the cascaded half-band filter RTL generation module reads the design parameters, and automatically generates cascaded half-band filter RTL code based on Python, and transfers the RTL code to the cascaded half-band filter test platform generation module; the cascaded half-band filter test platform generation module reads the generated half-band filter RTL code, and automatically generates a cascaded half-band filter test platform based on Python and Matlab. The present invention provides an automatic generation solution for the parameter design, RTL design, and test platform design of a cascaded half-band filter, and has broad development space.