7 results about "Half-band filter" patented technology

The invention discloses a high-order digital decimation filter with a variable decimation multiple, which comprises a cascade comb filter used for downsampling and anti-aliasing filtering, filtering high-frequency components and obtaining low-frequency density signals, and a compensation filter connected to the output end of the cascade comb filter and used for compensating passband attenuation and performing double decimation on the signals, and the output end of the compensation filter is connected with a half-band filter for realizing third-stage signal extraction. The invention further discloses a filtering method of the high-order digital decimation filter with the variable decimation multiple. Aiming at the defects that a traditional single-stage FIR filter is high in hardware requirement, complex in design, high in filter order and not easy to implement and the like, and aiming at the defect that a CIC filter is insufficient in passband flatness, a CFIR compensation filter is used for compensation, and finally a half-band filter is used for frequency reduction.

The invention discloses a multi-modulation system carrier synchronization integrated judging and locking device for satellite-to-ground data transmission, and belongs to the field of satellite-to-ground data transmission. The device comprises an AD conversion module, a digital down-conversion module, a low-pass filtering module, a half-band filter bank module, a digital resampling module, a matched filtering module, a carrier phase tracking module, a carrier phase error calculation module, a timing error calculation module and a carrier synchronization judging and locking module. According to the invention, the carrier synchronization integrated locking judgment function of multiple modulation systems in a satellite-ground high-speed data transmission CCM transmission mode and a VCM transmission mode is realized, the adaptability of the device is improved, and the device is convenient to realize and popularize.

The invention discloses a digital baseband communication receiving link circuit and a data receiving method, and relates to the technical field of data communication, the circuit comprises a downsampling module, a code element shaping module, a code element synchronization module, a decoding module and a CRC verification module; the down-sampling module comprises a CIC down-sampling circuit and a half-band filter down-sampling circuit; the code element shaping module comprises a delay circuit, a level comparison circuit and a level overturning circuit; the code element synchronization module comprises an interpolator circuit, an error detection circuit, a loop filter, a numerical control oscillator and a sampling decision circuit; the decoding module comprises a decoding state machine circuit and a data judgment circuit; and the CRC verification module comprises a CRC mode control circuit, a CRC (Cyclic Redundancy Check)-5 verification circuit and a CRC-16 verification circuit. According to the invention, the inter-symbol interference and the bit error rate caused by the synchronization error are reduced, so that the accuracy and the signal-to-noise ratio tolerance of the received data are improved on the whole.

The application discloses a kind of digital filter structures for Σ-ΔADC downsampling, adopt full digital method to construct three-order single loop feedforward system, series integrated integral-comb cascaded filter, compensation filter and half-band filter.Integral-comb cascaded filter is composed of multistage integrator series recursion structure, support downsampling multiple programmable, improve parallelism and hardware utilization by moving delay unit position in advance.Compensation filter adopts odd-order integrator multi-branch parallel, reduce resource occupation, significantly improve processing speed;Half-band filter uses retiming technology to adjust coefficient position, reduce critical path delay, improve the highest frequency of system, while reducing the amount of calculation through symmetric structure and multiplexing extraction path, front extraction reduces the demand of operation rate and data loss.The application realizes low power consumption, low hardware consumption and high design flexibility of downsampling filter in Σ-ΔADC digital module.

Systems and techniques are provided for energy detection by a wireless communication device. A method includes filtering a received signal using a half-band (HB) filter with a configured cut-off frequency to obtain a filtered signal based on the received signal, wherein the HB filter is associated with a receiver of the wireless communication device, and the received signal comprises a wireless transmission received by the receiver. Information indicative of a power level can be determined corresponding to a detected energy associated with the filtered signal. Embodiments of the wireless communication device process the received signal according to the information indicative of the power level, before demodulated symbols become available from a receiver downsampling chain.

The invention discloses a high-speed data transmission demodulation device based on multi-GPU parallel processing, and belongs to the technical field of satellite-ground data transmission. The device comprises a digital down-conversion unit, a low-pass filtering unit, a half-band filter bank unit, a digital resampling unit, a complex filtering unit, a digital AGC unit, a data extraction unit, a carrier Doppler frequency offset estimation unit, a forming coefficient storage unit, a coefficient convolution unit, a coefficient interception unit, a control word scanning unit and a carrier phase error compensation unit. A timing error calculation unit, a carrier phase error calculation unit, an error accumulation unit, and an error weighting unit. The method has the characteristics of high implementation reliability, high stability, low implementation complexity and the like.

The invention discloses a reconfigurable half-band cascade metering method, a chip architecture and a chip, and the metering method comprises the steps: carrying out the improvement of a metering method of an existing CIC architecture, replacing all low-pass filters with half-band filters HBF, and carrying out the metering of an input signal through employing the improved metering method; the chip architecture is used for realizing the recording method and specifically comprises an analog ADC (Analog to Digital Converter), the first processor, a first SPI (Serial Peripheral Interface) module, a first register, a random access memory, a second processor, a second register, a second SPI module and a third register, the chip adopts the chip framework; according to the method, the problem of relatively large metering errors is solved, the method and the architecture are proved to have excellent operation capability and extremely low hardware implementation cost in a power grid frequency fluctuation scene, and meanwhile, the method and the architecture have relatively high reconstruction flexibility to face complex multi-metering application scenes.