116 results about "Quantum wire" patented technology

The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.

In a semiconductor device, concave sections in which an opening area becomes small in proportion as a depth becomes deep are formed in a crystal layer, and a quantum structure is formed on at least one crystal face of a bottom section of the concave section and a border formed between plural sidewalls thereof. In case the quantum structure is formed in the bottom section, a quantum box is formed therein. If the quantum structure is formed in the border between the sidewalls of the concave section, a quantum wire is formed therein. In case the quantum structure is formed in the sidewall of the concave section, a two-dimensional quantum well is formed therein.

While a silicon substrate is heated, gold is evaporated thereon at a thickness of 0.6 nm, whereby melted alloy droplets are formed on the substrate surface. Then, the silicon substrate is heated to 450.degree.-650.degree. C. in a silane gas atmosphere of less than 0.5 Torr. As a result, a silane gas decomposition reaction occurs with the melted alloy droplets serving as catalysts, whereby silicon wires grow on the substrate surface. Subsequently, the metal alloy droplets at the tips of the silicon wires are removed and surface portions of the silicon wires are oxidized. Resulting surface oxide films are thereafter removed. As a result, silicon quantum wires that are thinner by the thickness of the surface oxide films are obtained.

A solid-state field-effect transistor device for detecting chemical and biological species and for detecting changes in radiation is disclosed. The device includes a quantum wire channel section to improve device sensitivity. The device is operated in a fully depleted mode such that a sensed biological, chemical or radiation change causes an exponential change in channel conductance of the transistor.

A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.

The current invention provides a method of fabricating quantum confinement (QC) in a solar cell that includes using atomic layer deposition (ALD) for providing at least one QC structure embedded into an intrinsic region of a p-i-n diode in the solar cell, where optical and electrical properties of the confinement structure are adjusted according to at least one dimension of the confinement structure. The QC structures can include quantum wells, quantum wires, quantum tubes, and quantum dots.

A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths, which pass energy to quantum structures. Quantum structures may include quantum dot particles on the surface of the fiber or electrodes on top of barrier layers and a transport layer, which form quantum dot devices. The energy passing through the control paths drives charge carriers into the quantum dots, leading to the formation of “artificial atoms” with real-time, tunable properties. These artificial atoms then serve as programmable dopants, which alter the behavior of surrounding materials. The fiber can be used as a programmable dopant inside bulk materials, as a building block for new materials with unique properties, or as a substitute for quantum dots or quantum wires in certain applications.

The invention discloses a method for controllable generation of quantum dots or quantum wires, which belongs to the field of preparation of low-dimensional quantum materials. The method comprises the following steps: arranging a substrate for growing the quantum dots or the quantum wires in solution with dissolved the quantum dots or the quantum wires and arranging an electrode which is in contact with the lower surface of the substrate on the bottom surface of the substrate; applying voltage between the solution and the electrode for forming a steady electric field so as to enable quantum dot or quantum wire material in the solution to settle in the position where the electrode is located on the substrate under the action of electric field force of the steady electric field and grow the quantum dots or the quantum wires on the substrate in the position corresponding to the electrode; and adjusting the position of the electrode to control the growth positions of the quantum dots or the quantum wires on the substrate. The method is simple to operate and good in controllable effect; and according to the method disclosed by the invention, controllable growth in any quantum dot or quantum wire position can be realized, and a foundation is laid for processing and manufacturing of quantum devices.

Quantum wire is formed on the bottom of a V-shaped groove in a V-grooved substrate as a channel between source and drain electrodes or as at least part of the channel. A photocarrier accumulation region is provided within the quantum wire or at a position connected to or adjacent to the quantum wire for accumulating charges generated when light shines onto a photosensitive region that comprises at least a clad layer that covers the quantum wire. A recess is provided in the upper clad layer to localize the photocarrier accumulation region. As a result, it is possible to provide a photodetector that exhibits high sensitivity, high speed and low power consumption in an expanded wavelength region. It is also possible to provide a photodetector capable of constructing core portions thereof by one-time selective growth.

On a grooved semiconductor substrate having a plurality of V-grooves individually extended in directions perpendicular to a direction Is of advance of an oscillated laser beam and mutually disposed in parallel along the direction Is of advance of the laser beam, a plurality of quantum wires (11) are formed on the V-grooves by selective growth of a Group III-V compound. The plurality of quantum wires are adapted to serve as limited-length active layer regions mutually disposed in parallel along the direction Is of advance of the laser beam with a period of an integer times of a quarter wavelength in a medium of a laser active layer and individually corresponding to stripe widths of laser. Consequently, a quantum nano-structure semiconductor laser satisfying at least one, or preferably both, of the decrease of a threshold and the stabilization of an oscillation frequency as compared with a conventional countertype can be provided.

A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and/or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.

A negative resistance field-effect element that is a negative differential resistance field-effect element capable of achieving negative resistance at a low power supply voltage (low drain voltage) and also enabling securement of a high PVCR is formed on its InP substrate 11 having an asymmetrical V-groove whose surface on one side is a (100) plane and surface on the other side is a (011) plane with an InAlAs barrier layer (12) that has a trench (TR) one of whose opposed lateral faces is a (111) A plane and the other of which is a (331) B plane. An InGaAs quantum wire (13) that has a relatively narrow energy band gap is formed at the trench bottom surface as a high-mobility channel. An InAlAs modulation-doped layer (20) having a relatively wide energy band gap is formed on the quantum wire as a low-mobility channel. A source electrode (42) and a drain electrode (43) each in electrical continuity with the quantum wire (13) constituting the high-mobility channel through a contact layer (30) and extending in the longitudinal direction of the quantum wire (13) as spaced from each other, and a gate electrode (41) provided between the source electrode (42) and the drain electrode (43) to face the low-mobility channel (20) through an insulating layer or a Schottky junction, are provided. Owing to the foregoing configuration, a very narrow-width quantum wire whose lateral confinement size can, without restriction by the lithographic technology limit, be made 100 nm or less is usable as a high-mobility channel, whereby there can be obtained a negative resistance field-effect element that develops a negative characteristic at a low power supply voltage and enables securement of a high PVCR.

A laser system includes a laser diode with a low dimensional nanostructure, such as quantum dots or quantum wires, for emitting light over a wide range of wavelengths. An external cavity is used to generate laser light at a wavelength selected by a wavelength-selective element. The system provides a compact and efficient laser tunable over a wide range of wavelengths.

A quantum nanostructure semiconductor laser is provided that does not use a buried structure defined by etching and regrowth processes in the prior arts, and can be manufactured using a procedure that is simple and has good reproducibility. This helps to reduce the threshold current and provides good lasing wavelength stability. The laser has a stripe-shaped ridge with a plurality of V-grooves formed on a compound semiconductor substrate in the direction of laser beam emisson, with the V-grooves being arrayed in parallel, with each V-groove extending orthogonally to the direction of laser beam emission. On the ridge, an optical waveguide is provided that comprises a lower cladding layer, a plurality of quantum wires and an upper cladding layer formed in order by a crystal growth process. The quantum wires are formed to a finite length corresponding to the stripe width of the laser beam, and are each located at a position corresponding to a V-groove, thereby constituting the laser active region. The optical waveguide is trapezoidal in shape, and has a peripheral sidewall that is at least as high as a height at which the quantum wires are located, and is exposed or covered only by an insulation layer.

A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.