According to the
memory chip test circuit provided by the utility model, the first test loop and the second test loop are arranged in parallel in the second side channel of the first analog switch and can be used for testing different test items, and the register is arranged in the second test loop and can be used for testing the test items corresponding to the first test loop. Meanwhile, an address
signal of a next to-be-tested memory is sent to the second test loop in advance and is stored in the register, after a
test item corresponding to the first test loop is completed, the address
signal stored in the register can be sent out only by sending a switching instruction to the register, and the first analog switch is controlled to switch an input port of a corresponding channel; therefore, the address
signal updating
waiting time can be effectively shortened, the switching speed can be improved,
signal interference in the switching action of the first analog switch can be shielded, and the test reliability can be improved.