50results about How to "Shorting problem" patented technology

According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask. A conformal layer of Si3N4 is deposited onto the structure, then anisotropically dry etched until the thin SiO2 layer is exposed to form the Si3N4 spacers. Diffusion regions are formed in the substrate by ion implantation. A layer of BPSG is deposited onto the structure and planarized. Contact holes are formed to expose said diffusion regions and filled with a metal to create borderless metal contacts therewith.

An electrochemical device includes a plurality of unit cells, each having a first separator and a cathode and an anode positioned at both sides of the first separator, and a continuous single second separator interposed between adjacent unit cells in correspondence with each other in a laminated pattern and arranged to surround each unit cell. The first separator includes a heat-resisting porous substrate having a melt point of 200° C. or above and a first porous coating layer formed on at least one surface of the heat-resisting porous substrate and made of a mixture of a plurality of inorganic particles and a binder polymer. The second separator includes a polyolefin porous substrate and a second porous coating layer formed on at least one surface of the polyolefin porous substrate and made of a mixture of a plurality of inorganic particles and a binder polymer.

A rechargeable lithium-sulfur cell comprising a cathode, an anode, a separator electronically separating the two electrodes, a first electrolyte in contact with the cathode, and a second electrolyte in contact with the anode, wherein the first electrolyte contains a first concentration, C1, of a first lithium salt dissolved in a first solvent when the first electrolyte is brought in contact with the cathode, and the second electrolyte contains a second concentration, C2, of a second lithium salt dissolved in a second solvent when the second electrolyte is brought in contact with the anode, wherein C1 is less than C2. The cell exhibits an exceptionally high specific energy and a long cycle life.

A wire-bonding method for connecting a wire-bond pad and a chip is characterized in that a metal ball is disposed on the wire-bond pad such that a bonding wire can be electrically connected to the wire-bond pad and raised to a certain height by the metal ball. In this arrangement, the short circuit problem caused by two adjacent wire-bond pads and impact problem on a solder mask caused by a bond head of a wire bonder during a wire bonding process can be avoided. The present invention also provides a package having a structure formed by the above-mentioned wire-bonding method.

An LED filament lamp comprises a bulb shell and an LED filament component located inside the bulb shell. The LED filament lamp further comprises a driving board, a lamp holder bulb shell and an inside liner. The inside liner is a bulb shell structure made of insulating material and installed inside the lamp holder bulb shell. At least a part of the driving board is located inside the inside liner to make the driving board and the lamp holder bulb shell separate from each other. The LED filament component is electrically connected to the driving board and the lamp holder bulb shell is electrically connected to the driving board. The LED filament lamp has characteristic of simple structure.

A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.

A method of transferring imprint carbon nano-tube (CNT) field emitting source is disclosed. Firstly, cathode lines are screen printed on a substrate. Then a dielectric layer formation on the cathode lines and substrate is followed. Afterward, gate lines formed on the dielectric layer by screen printing are performed. Next a patterning process is carried out to form openings. Subsequently, an imprint negative mold is dipped with CNT paste and imprinted the CNT paste on the cathode lines through the openings. After drawing of pattern from the imprint mold, the CNT paste is cured by annealing. Since the emitting sources are formed through the imprint negative mold, as a result, the size and shape can be predetermined. Moreover, the intervals between gate line and the emitting source are readily control, which resolve the circuit short problem between gate and cathode. Consequently, the current density, brightness, and uniformity of the emitter sources are significantly improved.

A chip structure comprising a substrate, a conductive layer, a plurality of bumps and a trap layer is provided. The substrate has a plurality of pads and the conductive layer is disposed on the pads. The bumps are disposed on the conductive layer above the pads and the trap layer is disposed between two adjacent bumps. In addition, a process of fabricating the chip structure is provided.

An electrically conductive material used in the formation of heat-releasing filled via holes in an electronic component-incorporated multilayer circuit board with a heat radiation member, in which the electrically conductive material comprises metal particles as a conductive metal which is a mixture of a first conductive metal consisting of silver (Ag) or copper (Cu) and a second conductive metal consisting of tin (Sn), and a ratio of the atomicity of tin to the atomicity of silver or copper and tin is 27 to 40%, and an electronic device using the same.

An apparatus and method apparatus and / or computer software to automate testing of a voice self service platform. In its software embodiment, the present invention comprises software that runs on the windows platform to simulate all the components of an Interactive Voice Recognition Unit (VRU). In addition this embodiment can also be used as a helper unit to test individual components of an interactive voice recognition (IVR).

A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

A method of fabricating an electrical connecting structure of a circuit board is disclosed. The method includes: providing a circuit board having a plurality of first and a plurality of second conductive pads; forming on the circuit board a solder mask having a plurality of openings to thereby expose the first and the second conductive pads; forming an metal adhesive layer on the first and the second conductive pads; forming a conductive layer on the circuit board and the metal adhesive layer; forming on the conductive layer a resistive layer, wherein a plurality of openings are formed in the resistive layer to expose the conductive layer on the second conductive pads; forming a metal post by electroplating through the conductive layer on the second conductive pads; removing the resistive layer and the conductive layer covered underneath; and forming a soldering layer on the metal post. This invention discloses a method of forming different connecting elements on a circuit board.

A semiconductor package substrate proposed by the invention includes a base body and a plurality of finger pads disposed on surface of the base body, wherein the finger pads are arranged in such a way that an angle is formed between connecting line of centers of two adjacent finger pads and the direction in which the finger pads are arranged. The finger pads are waterdrop shaped finger pads with arc ends and angle ends alternately disposed on surface of the substrate, alternately disposed waterdrop shaped finger pads and arc shaped finger pads, or alternately disposed arc shaped finger pads at a predetermined spacing. According to the present invention, distance between adjacent finger pads is reduced and problem of short circuit as a result of erroneous contact between bonding wire and adjacent finger pad is prevented.

A method of fabricating an electrical connecting structure of a circuit board is disclosed. The method includes: providing a circuit board having a plurality of first and a plurality of second conductive pads; forming on the circuit board a solder mask having a plurality of openings to thereby expose the first and the second conductive pads; forming an metal adhesive layer on the first and the second conductive pads; forming a conductive layer on the circuit board and the metal adhesive layer; forming on the conductive layer a resistive layer, wherein a plurality of openings are formed in the resistive layer to expose the conductive layer on the second conductive pads; forming a metal post by electroplating through the conductive layer on the second conductive pads; removing the resistive layer and the conductive layer covered underneath; and forming a soldering layer on the metal post.

An electroluminescent display device can include a substrate having a display area and a pad region; a thin film transistor in the display area; first and second pads in the pad region; an insulating layer covering the thin film transistor and the first and second pads; first and second pad contact holes exposing the first and second pads, respectively; a light-emitting diode electrically connected to the thin film transistor and including first and second electrodes and a light-emitting layer interposed therebetween; and first and second auxiliary pads on the insulating layer, the first and second auxiliary pads being electrically connected to the first and second pads, respectively, in which each of the first electrode and the first and second auxiliary pads includes a first layer formed of a transparent conductive material and a second layer formed of a metallic material, and a surface length between the first and second auxiliary pads is greater than a distance between the first and second auxiliary pads.

A processing unit, method, and device for vehicle air conditioner warning are disclosed. The processing unit is configured to judge a ventilation state of the current vehicle location based on positioning satellite signals, to judge an operation state of the vehicle engine based on information, to judge a running state of the vehicle based on information received, to judge a using state of the air conditioner based on information, to judge a vehicle door / window opening / closing state based on information, and to determine that there is a potential risk of poisoning and initiate the warning element when all the following conditions are met: the ventilation state at the current vehicle location is bad, the engine is in operation, the vehicle is in a stopped state or runs at a low speed, the air conditioner is being used, and all the doors and windows of the vehicle are closed.

A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a plurality of scan lines and a plurality of source lines are disposed on the substrate and define a plurality of pixel regions. A plurality of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A plurality of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and / or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and / or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.

In the manufacture of an integrated circuit, a first electrode (48) is formed on a substrate (28). In a first embodiment, a strontium bismuth tantalate layer (50) and a second electrode (52) are formed on top of the first electrode (48). Prior to the final crystallization anneal, the first electrode (48), the strontium bismuth tantalate layer (50) and the second electrode (52) are patterned. The final crystallization anneal is then performed on the substrate (28). In a second embodiment, a second layer (132) of strontium bismuth tantalate is deposited on top of the strontium bismuth tantalate layer (50) prior to the forming of the second electrode (52) on top of the first and second layers (50), (132). In a third embodiment, a carefully controlled UV baking process is performed on the strontium bismuth tantalate layer (50). In a fourth embodiment, an additional rapid thermal annealing process is performed on a substrate subsequent to the patterning process and prior to the final crystallization annealing process.

A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.

A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.

An array substrate and a display device, which can solve the technical problem of short circuit of transparent electrode and the failure of detection thereof, are provided. In the array substrate, each pixel unit comprises a primary pixel electrode, a secondary pixel electrode, and a voltage dividing capacitor. The voltage dividing capacitor comprises a common terminal electrode and a voltage dividing terminal electrode. The primary pixel electrode, the secondary pixel electrode, and the common terminal electrode are located at the same layer.

Provided are a light emitting device, a method for manufacturing same, and a display device including the light emitting device. The method for manufacturing the light emitting device comprises the steps of: preparing a lower substrate including a substrate and a buffer semiconductor layer formed on the substrate, forming an element rod by forming a separating layer disposed on the lower substrate, forming a first conductivity type semiconductor layer, an active material layer, and a second conductivity type semiconductor layer on the separating layer, and etching the first conductivity type semiconductor layer, the active material layer, the second conductivity type semiconductor layer, and the separating layer in a direction perpendicular to the lower substrate, forming a first insulating layer surrounding an outer circumferential surface of the element rod, forming a second insulating layer surrounding an outer circumferential surface of the first insulating layer and separating the element rod from the lower substrate to form a light emitting element.

The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.

An embodiment of the present invention provides an actuator module which can be equipped with a motor, a reduction gear and a control circuit, the actuator module comprising: a first housing which can have an active shaft, connected to a motor, pass through and be coupled thereto; and a second housing which is coupled to the first housing and has a passive idler horn, provided in a position in correspondence with the active shaft, pass through and be coupled thereto, wherein the idler horn has interposed a tube-shaped bearing, having a hollow portion formed in the center thereof, is coupled to a side of the second housing, and can have a cable connected into the second housing through the hollow portion of the tube-shaped bearing.

Provided are a light-emitting element, a manufacturing method thereof, and a display device comprising the light-emitting element. The method for manufacturing the light-emitting element comprises the steps of: preparing a lower substrate including a substrate and a buffer material layer formed on the substrate, forming a separating layer disposed on the lower substrate and including at least one graphene layer, forming an element deposition structure by depositing a first conductivity type semiconductor layer, an active material layer, and a second conductivity type semiconductor layer on the separating layer, forming an element rod by etching the element deposition structure and the separating layer in a vertical direction; and separating the element rod from the lower substrate to form a light emitting element.

A package apparatus includes a first package module, a second package module and multiple conductive elements. The first package module includes a first molding compound layer, a first conductive pillar layer disposed in the first molding compound layer, a first internal component, and a first protection layer. The first internal component electrically connects to the first conductive pillar layer and disposed in the first molding compound layer. The first protection layer is disposed on the first molding compound layer and the first conductive pillar layer. The second package module includes a second molding compound layer, a second conductive pillar layer disposed in the second molding compound layer, and a second internal component. The second internal component electrically connects to the second conductive pillar layer and disposed in the second molding compound layer. The conductive elements are disposed between the first and the second conductive pillar layers.

The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.

A method of transferring imprint carbon nano-tube (CNT) field emitting source is disclosed. Firstly, cathode lines are screen printed on a substrate. Then a dielectric layer formation on the cathode lines and substrate is followed. Afterward, gate lines formed on the dielectric layer by screen printing are performed. Next a patterning process is carried out to form openings. Subsequently, an imprint negative mold is dipped with CNT paste and imprinted the CNT paste on the cathode lines through the openings. After drawing of pattern from the imprint mold, the CNT paste is cured by annealing. Since the emitting sources are formed through the imprint negative mold, as a result, the size and shape can be predetermined. Moreover, the intervals between gate line and the emitting source are readily control, which resolve the circuit short problem between gate and cathode. Consequently, the current density, brightness, and uniformity of the emitter sources are significantly improved.