The invention provides a
time sequence optimization method based on unit movement and incremental rewiring, which is used for improving the
time sequence performance of a circuit through a
heuristic local optimization strategy on the premise of not changing a logic
netlist structure. The method comprises the following steps: firstly, preprocessing
layout and wiring of a circuit, generating an initial wiring topology, and improving the quality of an initial solution through congestion-driven wiring reconstruction; then, the movable units are divided into a plurality of batches, a multi-thread parallel mechanism is adopted, a local rewiring
algorithm based on A * search is executed in each small batch, and unit moving and wiring updating are completed; then
pruning is carried out on the moving area based on the median frame principle, and the wiring efficiency and the
gain evaluation precision are improved; and the wiring
gain is estimated through a
lookup table technology to assist in selecting candidate positions. For a redundant
network structure generated after unit movement, a selective rewiring mechanism is introduced in the method, and local repair and optimization are carried out on related networks. In order to ensure the legality of the solution, a unit playback strategy based on wiring revenue and post-
processing optimization driven by wiring length are finally adopted. Experimental results show that on the premise of keeping
connectivity and rule constraints, the method obviously optimizes the negative
time sequence margin (WNS / TNS) and the
bus length, is suitable for time
sequence optimization tasks after
integrated circuit layout, and has good convergence and expandability.