81results about How to "Extended rise time" patented technology

An air conditioner that comprises an exhaust heat recovery unit 3 for recovering exhaust heat in a heat transfer medium, a heat transfer medium passage 5a in which the heat transfer medium outputted from the exhaust heat recovery unit 3 flows, an auxiliary heating device 7, which is provided in the heat transfer medium passage 5a, for heating the heat transfer medium, an absorption chiller 9, to which the heat transfer medium passage 5a is connected, to be driven by heat of the heat transfer medium, a refrigerant passage 11a, through which a refrigerant outputted from the absorption chiller 9 flows, an indoor unit 13 to which the refrigerant is supplied through the refrigerant passage 11a, a heat transfer medium temperature detecting means 15 for detecting the temperature of the heat transfer medium flowing through the heat transfer medium passage 5a, a refrigerant temperature detecting means 17 for detecting the temperature of the refrigerant flowing through the refrigerant passage 11a, and a control portion 19 for controlling an operation of driving the auxiliary heating device 7. With this configuration, on startup, the control portion 19 controls an operation of driving the auxiliary heating device 7 according to the temperature of the heat transfer medium, which is detected by the heat transfer medium temperature detecting means 15, that when the temperature of the refrigerant, which is detected by the refrigerant temperature detecting means 17, is equal to or lower than a predetermined temperature, the control portion 19 decides that a startup operation is completed. Upon completion of the startup operation, the control portion 19 controls an operation of driving the auxiliary heating device 7 according to the temperature of the refrigerant, which is detected by the refrigerant temperature detecting means 17.

System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

A branching unit, for use in optical communication systems, has three branches A, B and C each including a connection for a power feed and several inputs/outputs for optical fibers. Optical switches are provided for selectively coupling inputs/outputs of different branches to enable a routeing of optical signals through the unit. The routeing is effected in dependence upon the way in which each of the three branch connections are provided with an electrical power feed.

A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.

The invention discloses a resonant gate driving circuit suitable for a high-frequency application. The resonant gate driving circuit comprises a resonant capacitor Cr, a resonant inductor Lr, an auxiliary switching tube 1, an auxiliary switching tube 2, a main switching tube 1, a main switching tube 2 and a main power device Q1. The resonant capacitor Cr is connected in series with the resonant inductor Lr, the resonant inductor Lr is connected to a source electrode of the auxiliary switching tube 1, a drain electrode of the auxiliary switching tube 1 is connected to a drain electrode of the auxiliary switching tube 2, a source electrode of the auxiliary switching tube 2 is connected to a source electrode of the main switching tube 1, a drain electrode of the main switching tube 2 and a gate of the main power device Q1, a drain electrode of the main switching tube 1 is connected to a positive power supply voltage VCC, and a source electrode of the main switching tube 2 is connected tonegative power supply voltage VEE. According to the driving circuit of the invention, the resonant capacitor Cr, the resonant inductor Lr and the four switching tubes S1, S2, S3 and S4 are used to achieve gate resonant driving, the driving circuit can recover gate driving power, the driving circuit loss is reduced, and the switch-on and switch-off times of the main power device are shortened.

A power supply device generates an output voltage by driving a piezoelectric transformer using a frequency signal. The power supply device includes a comparison unit configured to compare an output voltage and a voltage setting signal that sets the output voltage, and a voltage control oscillation unit configured to generate the frequency signal to drive the piezoelectric transformer based on comparison results of the comparison unit. The voltage control oscillation unit generates the frequency signal within a range between the resonant frequency and a spurious resonant frequency closest to the resonant frequency.

The invention discloses a device and method for eliminating POP noise of a CAPLESS audio power amplifier. In the device, a controllable resistance module is arranged between the audio power amplifier and an earphone; when the audio power amplifier is opened or closed, prolonging change time of bias voltage added on the earphone by controlling the resistance value of the controllable resistance module, so that the bandwidth of the POP noise generated by opening or closing the audio power amplifier can be reduced beyond hearing range. According to the invention, the controllable resistance module is controlled to prolong rise time or fall time of DC bias voltage on the earphone, that is, the change time of the bias voltage added on the earphone is prolonged, thus reducing the bandwidth of the POP noise caused by changing the DC bias voltage on the earphone so as to cause the bandwidth frequency to be reduced beyond the hearing range, thereby reaching the purpose of eliminating the POP noise.

Disclosed is a method for operating an electromagnetic flowmeter and a flowmeter. A measuring tube provided with a coil arrangement for producing a magnetic field at right angles to the direction of flow. The direction of current flow in the coil arrangement is altered periodically, and the current is kept essentially constant in one period after a rise to a predetermined value. the voltage applied to the coil arrangement and/or its derivative is determined and compared with an associated reference value. If this voltage or derivative does not fall below the reference value in a desired minimum time within a measurement period, an error message can be emitted in order to indicate a fault. If the voltage or derivative falls below the reference value, it is ensured that the magnetic field is sufficiently stable and measured values for a voltage which can be tapped off at measurement electrodes.

The invention relates to the field of coal slurry pretreatment, in particular to a multi-impeller mixed flow field ore pulp preprocessor based on ore pulp pipeline pressure drive. The multi-impeller mixed flow field ore pulp preprocessor comprises a mixing box, a driving rotary shaft and a driven rotary shaft. A driving gear is coaxially arranged on the driving rotary shaft, and a driven gear is arranged on the driven rotary shaft to form the meshing relation. A driving turbine is further coaxially arranged on the driving rotary shaft. A group of stirring impellers is fixed to the driving rotary shaft, and a group of stirring wheels is fixed to the driven rotary shaft respectively in a coaxial and mutual equal-height mode. In the vertical direction, the stirring impellers and projections of the stirring impellers produce intersections. A guide sleeve is arranged under the driving turbine. Guide blades are arranged inside the guide sleeve in a circinate mode, and the rotating direction of the mixed liquid guided by the guide blades is mutually identical to the rotating direction of the stirring impellers under the guide blades. The multi-impeller mixed flow field ore pulp preprocessor can play a very good hardening and tempering effect on floated coal slime, is especially suitable for slurry-mixing and quality-improving demands of fine coal difficult to float and is high in working efficiency, and the preprocessing process is quick and convenient.

A dual current switch detection circuit with selective activation is disclosed. In a particular embodiment, the switch detection circuit comprises an input node coupled to a switch to receive an input signal from the switch, a first current source coupled to the input node, a second current source coupled to the input node, and a detection circuit having an input coupled to the input node and an output coupled to the second current source to selectively activate the second current source.

A level shifter circuit 28 has a first buffer circuit 30 and a second buffer circuit 32, 34. An intermediate signal generated by the first buffer circuit 30 is directly passed to the second buffer circuit 32, 34 to control output of one of its output signal levels. A feedback signal generated in response to the input signal within the first power domain containing the first buffer circuit 30 is passed directly to the second buffer circuit 32, 34 to control the output signal level reaching the other of the output values. A feedback circuit comprising cross-coupled PMOS transistors 38, 40 is provided to boost the feedback signal level up to the voltage level of the second voltage domain which contains the feedback circuit 38, 40 as well as the second buffer circuit 32, 34. The level shifter circuit 28 has a low latency and a low static power consumption.

The invention relates to a charge pump circuit which comprises a boosting unit, a voltage division unit, a reference voltage source, a voltage comparison unit, a timepiece driver unit and an impulse modulation unit, wherein, the boosting unit is used for promoting the boosting voltage according to a modulation voltage output by the impulse modulation unit; the voltage division unit is used for carrying out voltage division on the boosting voltage output by the boosting unit and outputting the divided voltage; the voltage comparison unit is used for comparing the divided voltage with the reference voltage so as to provide a control voltage to the timepiece driver unit and the impulse modulation unit according to the comparison result; the timepiece driver unit is used for receiving the control voltage output by the voltage comparison unit, forming a driving voltage based on the control voltage and sending to the impulse modulation unit; and the impulse modulation unit is used for modulating the driving voltage sent by the timepiece driver unit according to the control voltage and sending a modulation voltage to the boosting unit.

The invention relates to a total cross-section inflatable floatation machine, comprising a flotation tank and a foam overflow mechanism arranged at the top of the flotation tank, wherein the tank body of the flotation tank is provided with an ore pulp inlet and an ore pulp outlet, the bottom of the tank body of the flotation tank is provided with a check valve mounting plate, and the shape of the check valve mounting plate is matched with that of the cross section of the bottom of the tank body of the flotation tank, thus the tank body of the flotation tank is divided into a pulp bearing chamber and an air chamber arranged below the pulp bearing chamber, one side of the bottom of the pulp bearing chamber is provided with an ore discharge port, one side of the air chamber is provided with an air inlet, and multiple check valves are uniformly distributed on the check valve mounting plate. The total cross-section inflatable flotation machine provided by the invention has a simple structure and is convenient to maintain, the ore dressing recovery percentage is improved, the energy consumption is reduced, gas is fully utilized, the chemical usage is reduced, the life of a quick-wear part is prolonged, the flotation process stage is shortened, and the equipment cost and investment of capital construction are reduced.

The invention relates to an air-suspending vibration signal inhibition-based method and system, a vibration signal of an air-suspending system and damping rate are analyzed by inputting designed improved negative pulse into a reshaper, a pulse sequence is obtained, the pulse sequence and a certain value of expectation are input to phase convolution to obtain a corresponding command and serve as motion system input of the air-suspending system, and inhibition of an air-suspending vibration signal is realized; the method has the advantages of improving rise time of the system and reducing the delay of motion response time of the system besides the characteristic of effectively inhibiting residual vibration of the air-suspending motion system, the improved negative pulse is input to the reshaper to obtain shorter delay time, and pulse number in the pulse sequence can be flexibly selected.

The present invention provides an output buffer providing multiple voltages including an arrangement of bootstrapping capacitors, and a charge replenishing mechanism which provides continuous pulses to the arrangement of bootstrapping capacitors, thereby, maintaining voltage on the bootstrapping capacitors.

The invention discloses an open-loop driving circuit for optimizing silicon carbide MOSFET turn-on waveform. The circuit comprises a driving voltage waveform generator for producing driving voltage waveform of a preset rising edge; a gate pole changing driving resistance control circuit for controlling the size of the gate pole driving resistance at different stages of the turn-on transient process, wherein the grid source voltage change rate of the silicon carbide is in consistent with the driving voltage rising change rate at the current rising stage, thereby controlling the current rising change rate and reverse current by controlling the driving voltage rising change rate; the gate pole current is increase at the voltage falling stage, thereby accelerating the voltage falling process and reducing the turn-on loss; the gate pole damping resistance is increased at the breakover-stabilizing stage, thereby suppressing the gate pole voltage overshooting without influencing the on-off speed. The driving circuit is simple in structure, easy to realize, low in cost, and capable of suppressing the reverse current peak and the gate pole voltage overshooting under the condition of reducing the turn-on loss.

A multi-level voltage output control circuit selectively outputs one of multi-level power voltages by driving gates of two MOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, the two output signals having complementary phases to each other and generated from two logic gates receiving two input signals which have an identical timing and complementary phases to each other, wherein the two logic gates advance or slow down a rising timing and/or a falling timing of the two output signals by differently adjusting a size of PMOS transistors and that of NMOS transistors, which construct the logic gates, thereby excluding a case in which the two output signals are in a same logic state at the same time.