6results about "Network simulating resistances" patented technology

An in-phase / quadrature (l / Q) clock generator (400) is described. The l / Q clock generated includes a poly-phase filter (420) configured to generate a four-phase quadrature clock signal (422) in response to a two-phase quadrature clock signal (406) generated in response to a single-ended input clock signal (402). The l / Q clock generated also includes a phase interpolator (460) configured to generate an output four-phase quadrature clock signal (462) from the four-phase quadrature clock signal. The l / Q clock generated further includes a poly-phase filter tune circuit (430) coupled to an output of the phase interpolator (460). The poly-phase filter tune circuit (430) is configured to generate a control voltage (432) for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.

A noise filter circuit includes a filter and a transistor off-resistance control circuit. The filter includes a first transistor and a charge storage component. The first transistor has off-resistance when turned off or operated under sub-threshold region. A control terminal of the first transistor is not directly tied to a reference voltage, and is used to receive a first control voltage. The charge storage component has one terminal coupled to a connection terminal of the first transistor. The transistor off-resistance control circuit is coupled to the first transistor, and arranged to set the first control voltage for controlling the off-resistance of the first transistor.

Hybrid computer module element X-(Cross)-point memory.

Server farm power management system.

An in-phase / quadrature (l / Q) clock generator (400) is described. The l / Q clock generated includes a poly-phase filter (420) configured to generate a four-phase quadrature clock signal (422) in response to a two-phase quadrature clock signal (406) generated in response to a single-ended input clock signal (402). The l / Q clock generated also includes a phase interpolator (460) configured to generate an output four-phase quadrature clock signal (462) from the four-phase quadrature clock signal. The l / Q clock generated further includes a poly-phase filter tune circuit (430) coupled to an output of the phase interpolator (460). The poly-phase filter tune circuit (430) is configured to generate a control voltage (432) for the poly-phase filter to tune the four-phase quadrature clock signal from the poly-phase filter.

A resistive attenuator and a method for improving linearity of the resistive attenuator are provided. The resistive attenuator includes a first transistor, an attenuation circuit and a compensation circuit, wherein both the first transistor and the attenuation circuit are coupled between an input terminal and an output terminal of the resistive attenuator, and the compensation circuit is coupled to the first transistor. The first transistor is configured to provide a first signal path between the input terminal and the output terminal. The attenuation circuit is configured to provide a second signal path between the input terminal and the output terminal, wherein signal attenuation of the second signal path is greater than signal attenuation of the first signal path. The compensation circuit is configured to compensate nonlinear distortion caused by the first transistor.