31results about How to "Add equivalent capacitance" patented technology

An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.

The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated.

The invention relates to controlling a device for converting charge into voltage comprising an amplifier and at least one capacitor mounted in inverse feedback between an input and an output of said amplifier, whereby said amplifier can be connected between at least one input stage, to receive a charge therefrom, and at least one output stage to deliver voltage thereto, said voltage being representative of the charge received at the input, said method comprising at least one phase comprising the voltage conversion of a charge received at the input. According to the invention the conversion phase comprises at least: one first sub-phase during which the amplifier is connected to the input stage and the amplifier is disconnected from the output stage; followed, by a second sub-phase during which the amplifier is disconnected from the input stage and the amplifier is connected to the output stage.

The present invention relates to a signal transmission structure, mainly including reference plane, combination pad, conductive wire and conductive ball. The signal transmission structure utilizes the change of the form of the reference plane or conductive wire to relatively reduce the equivalent capacity of thue conductive ball and its adjacent signal path or relatively raise the equivalent induction of the conductive ball and its adjacent signal path so as to compensate the high equivalent capacity between the conductive ball and reference plane, and can make the conductive ball and its adjacent signal path have the better impedance matching to raise the completeness of the signal after which is passed through the conductive ball and its adjacent signal path.

The invention provides a frequency selection surface with miniaturized low frequency number ratio, which mainly solves the technical problems that two resonant frequency points in low frequency band are far away from each other and the electric size of a unit is large on the existing dual-band frequency selection surface. The frequency selection surface comprises a dielectric plate (2),a metal patch (1) printed on an upper surface of the dielectric board and a metal patch (3) printed on a lower surface of the dielectric board,a metal through hole (4) and a metal connecting wire (5) connectingadjacent units, Each metal patch consists of four metal strips arranged on the surface of the dielectric plate. The first two metal strips form two resonant points of TE polarization and the second two metal strips form two resonant points of TM polarization. The four metal strips of the upper and lower metal patches are connected through metal vias to prolong the current path. The invention realizes good miniaturization effect while possessing low-frequency digital ratio characteristics, and can maintain stable performance for different polarization and angles, and can be applied to antenna sub-reflector of communication system and small communication equipment.

The invention discloses a multi-antenna MIMO system based on resonant ring decoupling structured. The system comprises a ground board, antennas, hollow-out grooves, first decoupling structures, second decoupling structures and feeding points, wherein the antennas are arranged in the hollow-out grooves in the edges of the ground board, and are welded to the ground board through the protruded feeding points on the hollow-out grooves; and the first decoupling structures and the second decoupling structures are same in structure and are resonant rings between the antennas on the ground board respectively, and each decoupling structure comprises a concave-type resonant ring, a first L-type resonant ring and a second L-type resonant ring, wherein one end of the concave-type resonant ring is connected with the first L-type resonant ring, and the other end of the concave-type resonant ring is connected with the second L-type resonant ring. The multi-antenna MIMO system solves the problem of poor isolation of a multiple-antenna system when applied to a miniature hand-held terminal, and enables the resonant ring decoupling structures to play a biggest role; through dual-ring superposition, band width of the resonant ring is expanded, thereby improving isolation of the MIMO system; and the structure is suitable for the multi-antenna system.

A self-luminous display pixel, comprising: a self-luminous circuit, the self-luminous circuit includes a self-luminous device; the self-luminous display pixel also includes an optical fingerprint sensing circuit, and the optical fingerprint sensing circuit includes a first TFT device and A photosensitive device; the channel layer of the first TFT device is located directly under part of the photosensitive device. The self-luminous display pixels can realize the fingerprint sensing function, and the overall structure is optimized.

The embodiment of the present invention provides a charging capacitor and a pump circuit, the charging capacitor is applied to the pump circuit of the memory, the first end of the charging capacitor is the leading end of the floating gate control electrode in a floating gate MOS transistor in the memory, and the second end of the charging capacitor is The two ends are the common end after the contact point of the P well in the floating gate MOS tube, the source electrode and the control grid are connected, and the power supply end of the charging capacitor is the leading end of the N well in the floating gate MOS tube. The charging capacitor in the embodiment of the present invention can not only withstand high voltage, but also has a large equivalent capacitance per unit area, which can realize fast and efficient charging.

A self-luminous display pixel, comprising: a self-luminous circuit, the self-luminous circuit includes a self-luminous device, and the self-luminous device includes a bottom electrode layer; the bottom electrode layer is a non-light-transmitting layer; the self-luminous display pixel It also includes an optical fingerprint sensing circuit, the optical fingerprint sensing circuit includes a first TFT device and a photosensitive device, and the channel layer of the first TFT device is located directly under part of the bottom electrode layer. The self-luminous display pixels can realize the fingerprint sensing function, and the overall structure is optimized.

A method for testing an A / D converter with a built-in diagnostic circuit with a user supplied variable input voltage includes generating a charge by a binary-weighted capacitor array responsive to an external voltage and a user specified code. The method further includes applying the charge to a first input of a voltage comparator and applying a bias voltage to a second input of the voltage comparator, and generating, by the voltage comparator, a comparison voltage responsive to the applied charge and the bias voltage. The method also includes applying the comparison voltage to an input of a successive approximation register and generating, by the successive approximation register, an approximate digital code responsive to the comparison voltage. The method also includes determining if at least one bit of the approximate digital code fails to toggle independent of adjacent bits.

An analog to digital (A / D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S / H) output. The A / D converter also includes a voltage comparator having a first input coupled to the S / H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S / H output and the bias voltage. The A / D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.

A tightly coupled miniaturized metamaterial structure of the present invention includes a dielectric substrate, a printed metal layer is provided on one end surface of the dielectric substrate, and a cross-shaped metal frame is provided on the other end surface of the dielectric substrate. There is also a coupling capacitor layer embedded in it. A tightly coupled miniaturized metamaterial structure of the present invention forms an inductance structure by using a cross-shaped metal frame, and utilizes the interaction between the embedded coupling capacitor layer and the printed metal layer in the dielectric substrate to form a parallel capacitor structure , resulting in a larger equivalent capacitance, thereby reducing the size of the metamaterial structure and realizing the miniaturization of the metamaterial.