3results about How to "Small equivalent capacitance" patented technology

The invention discloses a compact Marx generator based on an impact ionization semiconductor device, and relates to the field of a pulse power technology and a power semiconductor device crossing technology. Comprising N stages of sub Marx generators which are cascaded in sequence, and each sub Marx generator comprises an impact ionization semiconductor device, a first charging isolation element, a second charging isolation element, an energy storage unit, a first ground capacitor and a second ground capacitor; for any stage of sub Marx generator, the first end of the impact ionization semiconductor device is connected with the first end of the first charging isolation element, the first end of the first ground capacitor and the first end of the energy storage unit, the second end of the first ground capacitor is grounded, the second end of the impact ionization semiconductor device is connected with the first end of the second charging isolation element, and the second end of the second charging isolation element is grounded. The second end of the second charging isolation element is connected with the second end of the energy storage unit and the first end of the second ground capacitor, and the second end of the second ground capacitor is grounded. According to the compact Marx generator, the conduction safety is improved.

A data driver and a display device having the same are disclosed. The display device includes: a display panel configured to display an image and including pixels and data lines connected to the pixels; a timing controller configured to provide image data corresponding to the image; and a data driver including at least one output buffer configured to output an analog data voltage corresponding to the image data to a channel electrically connected to the data line. The output buffer includes: one or more transistors for applying a preset rising current or falling current to an output node connected to the channel to output a data voltage; and a capacitance adjustment circuit configured to adjust a capacitance of the output node based on a magnitude or rate of a data voltage change between adjacent pixel rows.

This invention discloses a heterojunction bipolar transistor and its fabrication method. The heterojunction bipolar transistor includes, from bottom to top, a substrate, a sub-collector region, a tunneling structure, a collector region, a base region, an emitter region, an emitter capping layer, and an ohmic contact layer. The tunneling structure comprises alternating layers of first and second conductivity types of ion doped layers. According to the heterojunction bipolar transistor and its fabrication method provided by this invention, by forming a tunneling structure composed of alternating layers of first and second conductivity types of ion doped layers between the sub-collector region and the collector region, an etch stop layer is no longer formed. The tunneling junction capacitance (Ctj) is connected in series with the collector junction capacitance (Cbc), reducing the equivalent capacitance and improving device performance.