The invention relates to a method for preparing a plurality of
layers of superfine
silicon lines. The method comprises the following steps: preparing a
silicon etching masking layer; extending to form Fin and source drain regions on two ends of the Fin; and forming the plurality of
layers of superfine
silicon lines. The method has the advantages that the positions of the superfine lines can be accurately defined through the deposition of an atomic layer, and the
controllability is good; the
anisotropy etching on silicon stops automatically, a
process window is large, and the sections of nano lines obtained by
etching are uniform and smooth in appearance; the process for forming a plurality of
layers of side wall etching masks by a method of firstly preparing masks and then extending a channel is simple, and the plurality of layers of side wall masks can be obtained only by one etching of the extension window regardless of the number of masking layers; the lines with sizes of less than 10nm can be prepared by combining oxidization technology, thus meeting the requirement of the key process of small-sized devices;
polycrystalline silicon can be subjected to wet etching with a TMAH solution, and the operation is simple, convenient and safe;
metal ions are not introduced, and the method is applicable to the
integrated circuit manufacturing technology; the method is entirely compatible with a bulk silicon planar
transistor process, and the process cost is small.