The invention relates to an SPI
verification method based on UVM
verification methodology, which is characterized in that a
verification platform is constructed by adopting the UVM verification methodology and a
system-level
hardware description language, and function verification is implemented on an SPI module. The verification platform comprises: a verification platform, a
test case test, a virtual excitation generation module vsqr, the APB
system environment is apb _ env; the APB configures a module apb _ master _ cfg, and the module apb _ master _ cfg is connected with the APB; the APB agent module is an apb _ master _ agt, and the APB agent module is an apb _ master _ agt; the SPI environment is spi _ env; the SPI configures a module spi _ cfg; the SPI agent module is set as spi _ agt; an SPI register model spi _ reg _ mdl, the
system comprises a format conversion module, an excitation generation module, an excitation driver module, a response collection module, a monitoring module, and a result comparison module. The format conversion module comprises an
adder, an excitation generation module, an excitation driver module, a response collection module, a monitoring module anda result comparison module. According to the invention, a UVM verification methodology is adopted to realize high hierarchy; a verification platform with high
reusability can generate various types of randomized data packets under the constraint condition, traversal of all addresses and instructions is achieved, the self-checking functions of automatic report collection, result comparison and thelike with the function coverage rate are achieved, and the verification efficiency and the verification reliability are improved.