36results about How to "Simplify layout and routing" patented technology

This invention relates to an error-check and error-correction code circuit for storages and a method for reading and writing data by it taking matrix G as a logic core including: a decoding process and a coding process and a method for writing in data by this method. Apart from a decoding process and an error correction process, it also includes a coding process, and finally puts forward an error check and correction and coding circuit for realizing said two methods including a decoder, an error-correction circuit, a coding circuit, an interface circuit and related data transmission circuit so as to simplify layout of bottom circuit and speed up operation speed of circuits.

The invention relates to a wireless sensor network system used for environmental monitoring inside a spacecraft. The wireless sensor network system comprises: a local network, that is, a data collection and transmission network, which employs a wireless networking technology to collect and transmit an environmental parameter inside a spacecraft; a gateway, which is used for carrying out bridging between the local network and a spaceborne data network/bus so as to realize data exchange between the local network and the spaceborne data network/bus; the spaceborne data network/bus, which is used for realizing communication between terminals on the bus and between a terminal and a spaceborne computer; and the spaceborne computer, which is used for carrying out processing on sensor data collected by the local network and emitting an appropriate instruction according to a result.

The invention discloses an autonomous reconstruction soft configuration method for a SoPC chip. The autonomous reconstruction soft configuration method is obtained by researching an autonomous reconstruction soft configuration circuit technology of the SoPC chip. According to the autonomous reconstruction soft configuration method, the characteristic that configuration interfaces are controllable is fully used, the GPIO interface of a processor is connected with the configuration interface of an FPGA chip, a physical data path and a configuration link are constructed, time sequence configuration and data configuration are achieved through control over signal output and collection of the GPIO interface and level fluctuations of the interfaces, and then autonomous reconstruction is completed. Compared with a traditional reconstruction configuration method, autonomous reconstruction of a system can be achieved without additionally arranging a special configuration chip for an FPGA in the SoPC chip, the size of the SoPC chip is effectively reduced, few signals for controlling autonomous reconstruction exist in the SoPC chip, and therefore the designing complexity is lowered.

The invention relates to a self-supply circuit for a flyback power converter. A bus voltage supply module supplies power to a control chip after the bus is powered on. After the control chip is powered on, the primary winding of the transformer is controlled to work by the power supply control module, and the secondary auxiliary winding of the transformer obtains voltage from the coupling of the primary winding to supply power to the secondary winding of the transformer. The power supply module of the secondary winding of the transformer is charged to supply power to the control chip. The switching module turns off the power supply output of the bus voltage supply module to the control chip after the secondary winding power supply module of the transformer is fully charged. After the powersupply module of the secondary winding of the transform is charged, The bus voltage is cut off, and the auxiliary winding supplies power to the control chip alone. If the power supply module of the secondary winding of the transformer fails or the PWM driving output duty ratio of the control chip is small, and the power supply control module is abnormal, etc., the fault recovery can be carried out, and the control chip can not be powered down.

The invention discloses a high-precision magnetic field detection and decoding circuit based on a CAN bus. Bipolar magnetic steel is designed and arranged in a rudder shaft, the magnetic steel rightlyfaces a magnetic coding chip, and the coding chip measures a rotating magnetic field; a special SSC interface is used for sending a measuring result to a main control chip MCU; and the MCU completesreceiving and decoding of the magnetic field to obtain a corresponding rotating angle of the rudder shaft. After the MCU completes calculation, digital signals are sent to a servo control circuit in real time through a CAN bus control module, and closed-loop control over a servo system is achieved. According to the high-precision magnetic field detection and decoding circuit based on the CAN bus,non-contact measurement of a system is achieved by adopting a non-contact measuring method based on magnetic field detection and decoding, and the working reliability of a product is improved. The difficulty of circuit design is greatly lowered based on a CAN bus communication mode, circuits can be implemented more easily in the distributing and wiring process, the space size of a circuit board can be effectively saved, and meanwhile the circuit design cost can be effectively saved.

The invention discloses a high-frequency and high-speed electronic circuit board based on a high thickness-radius ratio deep hole electroplating technology. The high-frequency and high-speed electronic circuit board comprises a master control board and a signal transmission module, wherein the master control board comprises a receiving chip and a driving chip and adopts a double-sided flexible circuit board, a polyester resin material is further arranged on an outer surface of the master control board, a printed circuit board with high reliability and relatively high flexibility is fabricated by taking the polyester resin material as a substrate, four holes are drilled in an upper right end of the master control board, an output end of the master control board is connected with a voltage regulation module and a rectification module, the voltage regulation module is connected with a pulse generation module through a receiving end signal detection module, a signal transmission module is connected with a signal detection module, and the signal detection module is connected with a DC-DC converter. The circuit board has high heat dissipation, light weight, miniaturization and thinness are achieved by reducing a size, so that a component device and a wire are integratedly connected.

The invention provides a partially-depleted silicon-on-insulator triode structure. The partially-depleted silicon-on-insulator triode structure comprises a buried oxygen layer, a collector electrode region, a base region, an ultra-shallow trench isolation region, a base electrode region and a collector electrode contact region, wherein the buried oxygen layer is arranged on a substrate, the collector electrode region is arranged on the buried oxygen layer, the base region is located on the collector electrode region, the ultra-shallow trench isolation region and the base electrode region are arranged on the two sides of the base region respectively, and the collector electrode contact region is arranged on the side, opposite to the base region, of the ultra-shallow trench isolation region; the doping concentration of the collector electrode contact region is larger than that of the collector electrode region, the collector electrode region is connected with the collector electrode contact region, and the collector electrode contact region, the ultra-shallow trench isolation region, the base region and the base electrode region are located on the surface of a silicon wafer. Moreover, the partially-depleted silicon-on-insulator triode structure further comprises a polycrystalline silicon emitting electrode arranged on the surface of the silicon wafer.

The invention discloses a layout and wiring method and device, equipment and a readable storage medium. According to the method and the device, for the functional module of which the data processing logic is matched with the star topology structure, the constraint modes with different constraint capabilities can be utilized to constrain each sub-module in the functional module to perform layout and wiring according to the star topology structure, so that each layout and wiring result is obtained; then, the layout wiring result meeting the preset index requirement is selected from all the layout wiring results to serve as the layout wiring scheme of the function module, layout wiring in the module can be simplified, the probability of occurrence of problems such as winding congestion, short circuit, time delay and function errors is reduced, line resources, chip power consumption and chip area are saved, and the production efficiency is improved. And a layout and wiring scheme meeting the preset index requirement can be selected, so that the performance, manufacturability and time sequence convergence effect of the chip can be improved. Correspondingly, the invention also provides a layout and wiring device, equipment and a readable storage medium, which also have the above technical effects.

The invention discloses a configuration method, device, processor and storage medium of electronic equipment. The method includes: determining a first register array in the electronic device, wherein the first register array is configured with a reset port; converting the first register array into a second register array, wherein the second register array is not configured with a reset port port; mapping the second register array as a memory; connecting the memory with an external circuit to obtain a configured electronic device, wherein the external circuit is provided with a third register array, and the third register array is configured with a reset port. The present invention solves the technical problem that the existing register array with a reset function cannot be mapped into a memory, thereby causing waste of chip resources of electronic equipment.

The invention provides a multi-concurrent RAM data transmission method and structure of an X-type link structure. The method comprises the following steps: mapping a plurality of physically independent sub-RAMs into a shared storage RAM; obtaining an interface corresponding to each core of the on-chip multi-core processor based on shared storage; arranging a multi-stage link transmission structurebetween the interface and the sub RAM, wherein each stage of link transmission structure is provided with a plurality of X-shaped structure routers; and forming a fixed transmission path between eachinterface and each sub RAM through the X-type structure router so as to send or respond to a data stream. According to the invention, the problem of difficult layout and wiring caused by too large area of the existing multi-concurrent RAM circuit and too complex arbitration circuit is solved, routing FIFO and arbitration circuit are not needed, so that the hardware resource overhead is small, only a small number of fan-in and fan-out x-type routers are provided, the layout and wiring are simplified, and the main frequency of the circuit is effectively improved.