42results about How to "Improve shutdown capability" patented technology

A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

Power semiconductor device having a wafer, including emitter and collector electrodes arranged on opposite sides, wherein a gate electrode arranged on the emitter side has a conductive gate layer and an insulating layer arranged in the following order between the collector and emitter side: a p doped collector layer, an (n−) doped drift layer, an n doped enhancement layer, a p based base layer having a first and second base region, and an (n+) doped first and second emitter layer, wherein the emitter electrode contacts the first emitter layer and the first base region at an emitter contact area, wherein the second emitter layer is insulated from a direct contact to the emitter electrode by the insulating layer and wherein the second emitter layer is separated from the first emitter layer by the base layer.

The invention relates to a gate commutated thyristor having a dual-p-base-region gate cathode structure and a preparation method thereof, and belongs to the technical field of semiconductor integrated circuits. The gate commutated thyristor comprises more than one chip cell. Each chip cell is composed of a p+ emitter electrode, an n' buffer region, an n- buffer region, a p base region 1, a p base region 2, a p+ short base region, an n+ emitter electrode, an anode metal electrode, a gate metal electrode and a cathode metal electrode. The p+ emitter electrode, the n' buffer region, the n- buffer region, the p base region 1, the p base region 2, the p+ short base region and the n+ emitter electrode are arranged in turn. According to the technical scheme of the invention, the gate metal electrode and the cathode metal electrode are ensured to be in the same plane with the surface of a silicon chip based on the conventional trenching process or the channeling abandonment process on the surface of the n+ emitter electrode and the gate electrode. The gate commutated thyristor is provided with an extra layer of p base region, so that the reverse breakdown voltage of a J3 junction is ensured to be larger. Furthermore, the voltage of an external reverse power supply is increased, so that the commutation speed is improved. The turn-off ability of GCT chips is improved.

An accumulation layer controlled thyristor, which belongs to the technical field of semiconductor power devices, is characterized in that the on / off of the thyristor can be controlled by stopping electron circulation through an electron barrier of an internal electric field formed in a P<+> bypass region and an N<-> depletion region. When a positive voltage is applied on a gate, an accumulation layer is formed at the interface between the N<-> depletion region (33) and a gate oxide layer (6); an electron inversion channel is formed in a P-type base region (8); and electrons pass through an N<+> active region (9), the accumulation layer, an N<+> layer (200), and the electron inversion channel to the an N<-> base region (3), thereby controlling the normal operation of the device. The accumulation layer controlled thyristor as the substitute of the conventional gate controlled thyristors, such as MOS controlled thyristors, has the advantages of lower conduction voltage drop, larger saturation current density, no parasitic effect, and greatly improved safety operation area, and can overcome the disadvantages of the conventional gate-controlled thyristors, such as the deficiency of current saturation characteristic and poor turn-off capability.

The present invention provides a high-voltage fast recovery diode structure, specifically a double-sided termination diode with a localized p+ doped region cathode structure, including an n-drift region, an anode region, a localized p+ doped cathode region and double-sided terminations area; the double-sided terminal structure includes a front terminal area and a back terminal area, respectively surrounding the anode area and the cathode area, which can improve the area efficiency of the terminal structure; the local p+ doping area is on the surface of the back cathode area Or inside, according to different application requirements, different dopant doses, widths, depths, and arrangement periods can be used, and holes can be injected at the end of reverse recovery to suppress electric field spikes and current filamentation on the cathode side, thereby solving the problem of double-sided termination. The resulting strong punch-through effect is not conducive to the improvement of the firmness and softness of the high-voltage fast recovery diode.

The invention discloses method for detecting the electrical reliability of a circuit breaker contact, and the method comprises the steps: 1, measuring a movement distance S1 before and after the switching of a circuit breaker operating mechanism; 2, continuously applying direct current to two ends of a circuit breaker single-phase arc-extinguishing chamber, and measuring a voltage Ui across two ends of the circuit breaker single-phase arc-extinguishing chamber and a current Ii flowing through the circuit breaker single-phase arc-extinguishing chamber in real time; 3, plotting changing curves of the voltage Ui and current Ii along with time t from the operation starting moment of the driving mechanism, wherein the changing curves specifically comprise a voltage (Ui)-time (t) curve and a current (Ii)-time (t) curve; 4, finding time T1 corresponding to a first peak, and calculating actual opening travels S2 of movable and static contacts; 5, judging the ablation degree of an arc-extinguishing chamber contact. The method solves a problem that the detection of the electrical reliability of the circuit breaker contact is not convenient.

The present invention provides a laser, especially a frequency doubling single direction overlapping output quasi-cw green laser in a full-solid T type double-cavity combined cavity, composed of two F-P, each F-P adopts flat-concave cavity structure, F-P adopts side pumped Nd:YAG crystal of the semiconductor laser pumped component having same model, each F-P is optimized design by computer simulation, a stably rotatable 1064nm fundamental frequency laser is formed in the F-P, each F-P obtains 532nm quasi-cw green laser by the audio-optical Q switching and frequency doubling technology, overlapping in the several frequency doubling crystals, reflecting by the harmonic reflector, obtaining secondary frequency doubling and output together. The whole system finally obtains 532nm green laser which power achieves 202W. The laser does not need any thermal len and thermal double refraction compensation element, having high output power, better beam quality, high doubling efficiency, better stability, widely applied in medical, industry.

The invention provides a gate drive circuit, an array substrate and a display device. Under the control of a signal inputted by an input terminal, a shift register transmits a clock signal of a first electrical level inputted by a second clock signal terminal to an output terminal in the first period of time, and transmits a clock signal of a second electrical level inputted by the second clock signal terminal to the output terminal in the second period of time. Under the control of a signal inputted by a first clock signal terminal, the shift register transmits a pull-down signal of the second electrical level to the output terminal in the second and third periods of time. Under the control of a signal inputted by a first reset terminal, the shift register stops transmitting the clock signal inputted by the second clock signal terminal to the output terminal in the third period of time. On this basis, the electric potential of a gate line can be pulled down together by the clock signal of the second electrical level and the pull-down signal of the second electrical level in the second period of time. Therefore, fast pulldown of the gate line is guaranteed and the power-off capability of a thin film transistor of a pixel unit and the charging capability of the pixel unit are further improved.