This invention belongs to the field of integrated
mask circuit generation technology, and provides a method and platform for generating and detecting integrated
mask circuits. The method involves obtaining an S-box configuration file,
parsing it, extracting the S-box, generating
hardware circuits from the extracted S-box, and obtaining an S-box file. A test environment is constructed based on the S-box file, and corresponding
test stimulus files are generated. Behavioral-level
simulation is performed in the test environment, and
simulation logs are recorded. The
simulation logs are parsed to determine whether the S-box design is functionally correct. The RTL-
level design of the S-box file is converted into a gate-level
netlist based on the target technology
library, generating a
netlist file and an area report. Timing
verification and power
estimation are performed under preset timing and load constraints, generating timing and power reports respectively. Multiple reports are synthesized, key performance indicators are extracted, structured, and a comprehensive evaluation report is generated. This invention can improve the design efficiency, reliability, and overall performance of
mask circuits.