30 results about "Pair gain" patented technology

A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

The embodiment of the present invention discloses a radio frequency power amplifier based on a transformer matching network, which includes an input matching network connected in sequence, a first-stage single-channel amplification circuit, a first-stage inter-stage matching network, a second-stage dual-channel amplification circuit, a second An inter-stage matching network, a third-stage four-way amplifier circuit, and an output matching network; the first inter-stage matching network includes a first transformer T1, and the second inter-stage matching network includes two second transformers T2. The output matching network includes two third transformers T3 and one fourth transformer T4; through the use of transformer matching in the inter-stage matching and output matching, the layout area is effectively reduced, and at the same time, no additional insertion loss is brought, and the gain and output The optimization effect of return loss has been significantly improved.

The invention discloses an interference signal suppression device, which comprises a low noise amplifier module, a signal conversion module, a signal processing module and a power amplifier module. Inputted radio frequency signals are processed by the low noise amplifier module, the signal processing module and the signal conversion module and are then amplified and outputted by the power amplifier module. The signal conversion module is used for carrying out gain control on the signals inputted by the low noise amplifier module, carrying out first conversion processing on the signals after gain control, outputting the signals to the signal processing module, carrying out second conversion processing on the signals outputted by the signal processing module and outputting the signals to thepower amplifier module. The signal processing module is used for controlling the signal conversion module for gain control and carrying out gain compensation processing on the signals after first conversion processing. The invention also provides a method of suppressing strong interference signals. According to the device and the method disclosed in the invention, the communication quality of network communication equipment can be improved, the reliability of a communication system is improved, and the effect of expanding the application scenario of the communication system can be achieved.

The systems and methods discussed herein provide for relative QoS gain measurement, and reduction in variance of QoS during bandwidth contention. In some implementations, the system measures relative QoS gains of, or penalties to, similar connections or network flows due to different factors that affect the transmission throughput and QoS. The system provides scheduling of packets on different connections or flows according to ratios of QoS penalties or gains on the connections or flows, preventing a well-performing connection or flow from cannibalizing throughput from under-performing connections or flows.

In described embodiments, process, voltage, temperature (PVT) compensation in a serializer / deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

The invention discloses a digital-to-analog converter (DAC for short) gain self-calibration circuit, comprising: a first counter counts the output clock of the crystal oscillator (XTAL for short), and controls the state jump of the DAC gain calibration circuit; the DAC control circuit outputs the DAC The frequency division circuit completes the frequency division of the voltage-controlled oscillator (VCO) output clock; the second counter completes the counting of the frequency division circuit output clock; the first lookup table outputs the preset frequency point corresponding to the DAC gain control word ; The second lookup table outputs the difference between the DAC gain control word at the target frequency point and the center frequency point; the fine-tuning control circuit outputs the DAC gain control word at the target frequency point. The present invention can change the capacitance value of the varactor in the inductor-capacitor oscillator by calibrating the DAC gain, finally change the frequency tuning curve of the VCO, and obtain the target frequency signal, and can also automatically Complete quick calibration of DAC gain for multiple frequency tuning curves.