The invention provides a non-contact
chip interconnection structure stress test method and
system, and relates to the technical field of
chip testing, and the method comprises the steps: generating an
energy source selection instruction based on the material attribute of a
chip interconnection structure, applying a dynamic load, and synchronously collecting an original
signal set which comprises a deformation response parameter and temperature field distribution; performing feature decoding on the deformation response parameter to generate a physical
feature vector; reconstructing a three-dimensional stress
tensor field according to the physical
feature vector and the temperature field distribution, and performing position marking in the reconstructed three-dimensional stress
tensor field to obtain a risk position coordinate set; generating a parameter optimization instruction based on the temperature rise distribution of the risk position coordinate set, feeding back the parameter optimization instruction, and performing parameter optimization; and carrying out dynamic function conversion and damage accumulation integration based on the three-dimensional stress
tensor field after parameter optimization, and outputting a quantitative life and risk position coordinate set. According to the method, the accuracy, the reliability and the comprehensiveness of the stress test of the chip
interconnection structure are remarkably improved.