37results about How to "Reduce photolithography steps" patented technology

The invention provides a display panel, which comprises a base plate. The base plate has a first reflecting layer and a second reflecting layer with specific light transmittance. The first reflecting layer comprises a reflecting unit array. Each reflecting unit comprises a reflecting plate which can continuously move along a direction perpendicular to the first reflecting layer, and a supporting beam connected with the reflecting plate and a connecting part. The invention additionally provides a display method, a display device and a color rendition method thereof. The display panel synthesizes color through time sequence color without distinguishing pixel color, the manufacturing process is only one third of the manufacturing process of a traditional display panel manufacturing method, the structure is simple and the manufacturing cost is low. The display device can compensate color drift caused by manufacturing error, the task of accurately realizing color rendition is transferred to the peripheral circuit of the display panel from the manufacturing process, and thereby the requirement on the precision of the manufacturing process is reduced.

The invention belongs to the technical field of microelectronic devices and memories, and discloses a three-dimensional stacked phase change memory and a preparation method thereof. The preparation method specifically comprises the following steps of preparing a multi-layer structure on which a horizontal electrode layer and an insulating layer are crossly stacked, on a substrate; then etching toform a groove and a discrete three-dimensional strip-shaped electrode; filling an insulating medium in the groove, forming small holes in the boundary area of the three-dimensional strip-shaped electrode and the insulating medium, sequentially depositing a phase change material on the walls of the small holes, and filling an electrode material in the small holes to prepare a vertical electrode, thereby obtaining the multi-layer stacked three-dimensional stacked phase change memory. According to the present invention, by improving the whole flow process of the preparation method, a three-dimensional phase change memory array can be established by utilizing the vertical electrode structure, and compared with the prior art, the problems of complex multi-layer stacking steps, high process implementation difficulty, unit size miniaturization and the like of an existing three-dimensional stacked phase change memory in process preparation, can be effectively solved.

The invention provides a semiconductor laser and a manufacturing method thereof. The semiconductor laser includes a semiconductor substrate and a resonator formed over the semiconductor substrate and containing a nitride semiconductor layer. A strain exerting on a region near the facet of the resonator is smaller than a strain exerting on the region between the regions near the facet.

The present invention relates to a manufacturing method of a thin film transistor array panel. The method includes forming a gate line including a gate electrode on a substrate, forming a first insulating layer on the gate line, forming a semiconductor layer on the first insulating layer, forming an ohmic contact on the semiconductor layer, forming a data line including a source electrode and a drain electrode on the ohmic contact, depositing a second insulating layer, forming a first photoresist on the second insulating layer, etching the second insulating layer and the first insulating layer using the first photoresist as an etching mask to expose a portion of the drain electrode and a portion of the substrate, forming a pixel electrode connected to an exposed portion of the drain electrode using selective deposition, and removing the first photoresist.

A thin film transistor and a method for fabricating the same. The thin film transistor comprises a substrate and a patterned semiconductive layer formed on the substrate, wherein the semiconductive layer comprises a channel region and doped regions adjacent to the channel region. A gate insulating layer is formed on the above structure. A gate electrode is located on the gate insulating layer above the channel region. Source and drain electrodes are located on the gate insulating layer adjacent to the semiconductive layer. A dielectric layer having contact holes is formed on the above structure and a patterned conductive layer is formed on predetermined parts of the dielectric layer electrically connecting the doped regions to the source and drain electrode through the contact holes.

The invention provides a gallium nitride device structure combining secondary epitaxy and a self-alignment process and a preparation method. The preparation method comprises the steps of: providing asemiconductor substrate; forming an epitaxial structure comprising a gallium nitride layer; forming a source structure and a drain structure through epitaxial growth under mask layer protection; forming a grid side wall; and forming a grid structure. According to the preparation method of the invention, the source electrode structure and the drain electrode structure are formed through secondary epitaxial growth, and therefore, ohmic contact resistance can be effectively reduced; the etching rate and material damage caused by etching are balanced through multi-step ion etching, oxidation and acid solvent digital etching before the secondary epitaxy, and process cost is considered while material quality is guaranteed; the self-alignment technology is adopted, errors caused by an alignment process in a photoetching process are avoided, and the size of a grid electrode is accurately defined; and the size of the grid electrode is controlled by utilizing the thickness of an isolation side wall, so that a grid pin photoetching step is omitted, and a technological process is simplified. With the preparation method adopted, the heteroepitaxy of GaN materials can be achieved on a large-sizewafer, and epitaxy cost per unit size is saved.

The invention discloses a thin film transistor. The thin film transistor comprises a substrate, a patterned light shielding layer formed on the substrate, an active layer formed on the light shieldinglayer, a gate dielectric layer formed on the active layer and a gate electrode formed on the gate dielectric layer, and a passivation layer formed on the active layer and the gate electrode, whereinthe light shielding layer adopts an insulating non-metal light shielding material; and the active layer comprises a channel, a source region and a drain region of the transistor. The invention also provides a preparation method of the thin film transistor.

The invention provides a method for manufacturing embedded source / drain MOS transistors. The method comprises the steps that gate structures are formed on a PMOS transistor area and an NMOS transistor area formed on a semiconductor substrate respectively, and an STI is arranged between the PMOS transistor area and the NMOS transistor area; channels adjacent to the two sides of each gate structure are synchronously formed on the PMOS transistor area and the NMOS transistor area; after first strained silicon grows in the channels of the PMOS transistor area and the NMOS transistor area, first embedded source / drain electrodes are synchronously formed; a barrier layer is disposed on the PMOS transistor area; after acid gas is used for etching the first embedded source / drain electrode in the NMOS transistor area so that second strained silicon can grow in the channels in the totally exposed PMOS pipe area, second embedded source / drain electrodes are formed; the barrier layer disposed on the PMOS transistor area is removed. According to the method, the existing technological steps of manufacturing the embedded source / drain MOS transistors can be optimized, and manufacturing cost can also be lowered.

The present application provides a method for preparing a semiconductor device, which relates to the technical field of semiconductor preparation technology. The method includes covering a wafer with a non-photosensitive material layer; covering the non-photosensitive material layer with a photosensitive material layer; forming a preset pattern on the non-photosensitive material layer to expose the wafer surface, wherein a first opening is formed on the photosensitive material layer, a second opening is formed on the non-photosensitive material layer, and the aperture of the first opening is smaller than the second opening. The diameter of the opening; forming a first depth groove on the exposed wafer; forming a second depth groove at the bottom of the first depth groove, wherein the width of the second depth groove is less than or equal to the width of the first depth groove; removing the wafer The remaining non-photosensitive material layer and photosensitive material layer. It can be formed by only one patterning process, which saves photolithography steps, reduces the steps of removing photoresist, and improves the preparation efficiency by reducing the number of photolithography times.

The invention provides a manufacturing method of a schottky diode with high performance; the manufacturing method comprises the following steps of: providing a semiconductor substrate, and sequentially forming a heavily doped layer and a lightly doped layer on the semiconductor substrate; depositing an insulating layer on the lightly doped layer, and forming an insulating layer window above the lightly doped layer; washing the exposed lightly doped layer by adopting a washing solution; depositing a first metal layer on the insulating layer and the lightly doped layer; alloying the first metal layer and the lightly doped layer, and forming an alloying layer between the first metal layer and the lightly doped layer; removing the first metal layer; forming an upper electrode on the alloying layer, wherein the washing solution mainly comprises the following components in percent by weight: 65-75% of phosphoric acid, 5-15% of acetic acid, 1-5% of fluoboric acid and 1-5% of nitric acid. According to the manufacturing method, before the first metal layer of the schottky diode is deposited, the specific washing solution is used for washing and slightly corroding the lightly doped layer so that particles, stains and interface detects remained on the surface are eliminated, a contact junction of a metal semiconductor becomes better, thereby the schottky diode has more efficient and stable performance.

The present invention provides a method for forming a semiconductor device, comprising: performing a first etching process, forming a second hard mask layer, a first hard mask layer, The first dielectric layer and the first groove of the composite nanosheet layer, the first groove extends into the substrate; a second dielectric layer is formed, and the second dielectric layer fills the first groove; removing The second hard mask layer to expose the first hard mask layer and the second dielectric layer higher than the first hard mask layer; forming a third hard mask layer, the third hard mask layer The mask layer covers the first hard mask layer and the top and sidewalls of the second dielectric layer; a self-aligned etching process is used to form through the adjacent regions of each N well region and P well region. The first hard mask layer, the first dielectric layer and the second groove of the composite nanosheet layer. A self-aligned etching process is adopted to reduce photolithography steps, reduce costs, and improve transistor performance.

The invention discloses a preparation method of a cathode isolation column of an organic electroluminescent device, which is completed by coating an organic insulating film, exposing once, and developing once. In this method, two adjacent raised columns are used to replace the original inverted trapezoidal isolation columns, so as to realize the effective isolation of adjacent pixel electrodes of the organic light-emitting device. The preparation method of the cathode isolation column in the organic electroluminescence device provided by the invention has the advantages of simplifying the process flow, saving development and corrosion materials, improving production efficiency, reducing environmental pollution, preventing device cross-effects, and the like.

The invention relates to the field of intelligent chips, in particular to a programming control circuit for a programmable chip. The programming control circuit comprises a plurality of data set units, a programming recognition unit and a switching unit. Each data set unit comprises a flag bit subunit and a plurality of programming data bit subunits; the programming recognition unit used for recognizing programming times is respectively connected with the flag bit subunit in each data set unit to recognize flag bit signals of the flag bit subunits and control the switching unit; the switching unit is connected with the programming data bit subunits of each data set unit and communicated with the corresponding programming data bit subunits under the control of the programming recognition unit to output corresponding programming data bit signals. The programming control circuit for the programmable chip has the advantages that programming for multiple times can be realized with no need of special processes, so that a step of photoetching in chip production is omitted, and cost is reduced; further, quantity of the data set units can be increased or decreased according to needs to realize programming for multiple times.

A forming method of a CMOS transistor comprises the steps that a semiconductor substrate is provided, and the semiconductor substrate comprises an NMOS area and a PMOS area; pre-decrystallization injection is conducted on the source region and the drain region of the NMOS area and the source region and the drain region of the PMOS area; the source region and the drain region of the NMOS area and the source region and the drain region of the PMOS area are etched to form a first opening, the depth of the first opening is smaller than the depth of pre-decrystallization injection, and an embedded source region and an embedded drain region of an NMOS are formed in the first opening; a blocking layer is formed, and the blocking layer is provided with a second opening exposing the PMOS area; the source region and the drain region of the PMOS area are etched along the second opening, the embedded source region and the embedded drain region of the NMOS and the pre-decrystallization injection area of the PMOS area are removed to form a third opening, and an embedded source region and an embedded drain region of the PMOS are formed in the third opening. The forming method of the CMOS transistor is simple in process.

A shielded gate MOSFET device and its preparation method. The present invention relates to power semiconductor devices. In order to solve the problem of cumbersome and costly preparation methods of existing shielded gate trench type field effect transistor devices, the present invention provides the following technology Solution: more than one parallel series of grooves located in the epitaxial layer, the series of grooves are composed of interconnected first-type grooves and / or second-type grooves, and the series of grooves pass through horizontal grooves designed in different forms Groove connection, there is more than one third-type groove surrounding the series of grooves on the periphery of the series of grooves. The shielded gate trench type field effect transistor device proposed by the invention has a unique structure and manufacturing process.