137 results about "Computational RAM" patented technology

A system and method are provided for placing network functions among respective locations in a network. The locations at which the network functions are placed can be nodes and network devices within the network. These nodes can be selected, e.g., based on which network devices have available capacity and or specialized hardware (e.g., accelerator sin a data processing units (DPUs)) that is optimized for particular network functions. The network functions can include an inline network function that is provisioned directly in a data plane of one of the network devices (e.g., in-lined directly in a hardware offload device without a virtual machine and without a container). The decision of where to place the network functions can be based on a performance metric (e.g., representing available computational / memory resources at the network nodes) and / or a network-function metric (e.g., representing consumed computational / memory resources by the network functions) to improve system performance.

A key-value cache management system processes inference requests of a generative model. An inference request requests a starting virtual memory address and a number of layers in the generative model. In response to receiving an inference request, contiguous virtual memory space is reserved for the key-value cache in accordance with the inference request by assigning the starting virtual memory address in the key-value cache and calculating memory pointers for each layer in the model and each block so that the one or more blocks are written sequentially. The generated memory pointers are outputted to the generative model so that each self-attention layer writes computed key-value pairs at physical addresses in the key-value cache specified by the memory pointers.

This application generally relates to memory provisioning and particularly describes systems and methods for distributed memory pools. For example, a computing / memory device in a distributed system may be configured to execute application logics using local cache for data maintained in non-local memory in another computing / memory device of the distributed system. The computing / memory device may further be configured to provide memory for other applications executed on other computing / memory devices of the distributed system. The local and non-local memory allocation for the applications in the computing / memory devices of may be dynamically and adaptively adjusted according to various system parameters and indicators.

An information transfer system may include: a master controller (XMC) configured to issue a command in the form of a memory protocol data packet, and wherein the master controller is configured to generate routing information indicating whether the memory protocol data packet is to be processed according to a first protocol or according to a second protocol different from the first protocol. The information transfer system may also include a slave controller (XSC) configured to receive the memory protocol data packet from the master controller, wherein the slave controller is configured to use the routing information to selectively cause the memory protocol data packet to be processed according to the first protocol or according to the second protocol.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

The invention discloses a large model training resource configuration optimization method for a cloud heterogeneous GPU cluster. The method comprises heterogeneous GPU resource configuration and resource perception stage deployment. A cost tree pruning mechanism is provided for resource configuration, a plan with low cost is searched preferentially, a configuration scheme is expressed as a tree path, meanwhile, a multi-dimensional pruning method is adopted to reduce unnecessary branches, and efficient GPU configuration is achieved. According to stage deployment, through defining a Compute-Memory Ratio (Compute-Memory Ratio, CMR), the requirements of each stage on the GPU computing power and memory capacity are considered in a combined manner, the communication and computing efficiency in the training process is optimized, and the large model training time is remarkably shortened. And finally, a large model training resource configuration optimization method Espresso oriented to the cloud heterogeneous GPU cluster is provided in combination with resource configuration and stage deployment strategies, and the user cost is reduced to the maximum extent while the training performance is ensured.

Dynamic provisioning of resources in a datacenter improves the utilization efficiency of compute, memory, storage, and network resources, while maintaining flexibility to meet changing demands. Embodiments herein disclose protocol-aware provisioning of resources over Compute Express Link (CXL) fabrics, enabling multi-protocol pooling and disaggregation of resources, including memory and workload-specific accelerators such as GPUs and DSAs. In some embodiments, a Resource Provisioning Unit (RPU) facilitates intent-based protocol translations and mappings between address spaces, potentially enabling the creation of large-scale compute-memory fabrics that may utilize both coherent and non-coherent Non-Transparent Bridging (NTB) between multiple protocols in a single system, serving as the underlying infrastructure for executing workloads such as Large-Language Models (LLMs) and Deep Learning Recommendation Models (DLRMs). Some embodiments also optimize low-latency communication between processes running on different nodes by enabling host-to-host memory provisioning for libraries such as OpenMP, Pthreads, or CUDA, which can utilize shared memory.

The invention aims to provide an efficient memory allocation and recovery method for an Android device, and relates to the technical field of memory processing, the method comprises the following steps: step 1: obtaining running data of the Android device, and calculating a memory state entropy based on the running data; calculating a memory fragment risk degree in combination with the priority matrix and the operation data; 2, calculating a memory allocation dynamic threshold according to the memory fragmentation risk degree; calculating a self-adaptive memory compression rate; step 3, using a self-adaptive memory compression rate to compress memory data which is not used by the Android device at present; the page number of the activity process is lower than the set minimum page threshold value; 4, if the memory fragmentation risk degree exceeds a set fragmentation threshold value, the Android device executes memory fragmentation; and averagely distributing the residual memory capacity to all the active processes. According to the invention, accurate allocation and efficient recovery of memory resources are realized.

The invention discloses a data processing method and system for a low-energy-consumption large language model based on a momentum mechanism and multiple types of experts, and belongs to the technical field of large language models, and the method comprises the steps: obtaining a hybrid expert model which comprises a gating network, a combination network and a plurality of expert networks; obtaining target data based on a lazy loading mechanism; obtaining fitness scores of the target data corresponding to the expert networks through the gating network, and obtaining the expert network meeting the sorting requirement as a target network; and obtaining output data of the target data in the target network, and carrying out weighted summation on the multiple output data through the combined network. According to the method, the multiple expert networks are arranged in the hybrid expert model, the fitness ranking is performed on the fitness scores of the target data, and the output of the expert network meeting the ranking requirement is selected to perform weighted summation so as to obtain the final output, so that the floating-point operation and calculation memory overhead are reduced, the calculation efficiency is improved, and the memory resource waste is reduced.

The invention provides a heterogeneous resource dynamic sensing and self-adaptive scheduling method, which comprises the following steps of: dynamically acquiring basic attributes such as resource types, core configuration, memory capacity and bandwidth and real-time information such as load state and temperature through a heterogeneous resource feature extraction module by utilizing a hardware interface and software probe technology, and storing data in a feature table after processing, accurate scheduling decision basis is ensured; a self-adaptive scheduling algorithm is designed, matching with resource characteristics is carried out based on task calculation, memory and parallelism requirements, proper resources are preferentially allocated, competition is avoided by checking a load state, and the algorithm supports dynamic adjustment so as to optimize allocation efficiency; and finally, through a real-time monitoring and dynamic adjustment mechanism, regularly collecting resource and task state information, detecting a competition or low-efficiency condition, executing operations such as task migration, priority adjustment or resource reservation and the like, and ensuring efficient operation of the system. The heterogeneous resource scheduling efficiency and stability are improved, and the method is suitable for a modern computing environment.

An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.

The invention relates to the technical field of signal processing, and discloses a multichannel data acquisition system and method based on an FPGA (Field Programmable Gate Array), an acquisition module drives a global counter by using a global synchronous clock, writes acquired data into an annular buffer area with a physical address and a counter value in a linear mapping relationship, and establishes implicit time index storage. When a trigger event occurs, the system broadcasts the locked global trigger timestamp, and the acquisition module backtracks and reads historical data according to the global trigger timestamp, and packages the historical data into a sparse matrix type data packet in combination with the channel validity mask. And after receiving the data packet, the data processing module directly calculates a memory mapping address by using global time information in the data packet, and writes a data load into a corresponding position of the waveform reconstruction buffer area. According to the method, through strict binding of the physical address and the absolute time, independent time label redundancy is eliminated, high-precision synchronization of distributed multiple channels is ensured, and out-of-order automatic in-situ recombination and efficient waveform reconstruction of data of a receiving end are achieved.

An integrated circuit device may include programmable logic circuitry on a first integrated circuit die and memory that includes compute-in-memory circuitry on a second die. The programmable logic circuitry may be programmed with a circuit design that operates on a first set of data. The compute-in-memory circuitry of the memory may perform an arithmetic operation using the first set of data from the programmable logic circuitry and a second set of data stored in the memory.

Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks, formed on a common substrate. The computational memory system also includes at least one local error correction code (ECC) module configured for calculating an original ECC based on received data, at least one local ECC module associated with at least one of the processor subunits and / or at least one of the memory banks.

The invention discloses a language model retrieval reasoning system and method based on high-speed intercommunication connection, and the system comprises a host, a high-speed intercommunication connection switch, a high-speed intercommunication connection memory pool, and an image processor, the high-speed intercommunication connection memory pool comprises a near memory calculation memory and a double data transmission rate memory, and the high-speed intercommunication connection switch comprises an adaptive partition module; wherein the host is respectively connected with the high-speed intercommunication connection memory pool and the image processor through the high-speed intercommunication connection switch; the host is used for receiving the first cue word, generating a second cue word and storing the second cue word to the double data transmission rate memory through the high-speed intercommunication connection switch; and the host is also used for extracting a second cue word from the double data transmission rate memory through the high-speed intercommunication connection switch for reasoning and determining a task allocation object in a reasoning stage by utilizing a self-adaptive partition module connected to the high-speed intercommunication connection switch, and the allocation object is a near-memory computing memory or an image processor.

The invention relates to a GPU-based high-IO perceptibility long-sequence text injection method, medium and equipment, and the method comprises the steps: obtaining and coding a long-sequence text input, processing a coded matrix vector through a multi-head attention mechanism, and realizing text injection, the matrix vector comprises a query Q, a key K and a value V. The method is characterized in that the value V is equal to the query Q, the key K and the value V. In the multi-head attention mechanism, the similarity is calculated by using an L2 distance, the matrix vector is segmented into blocks to realize thread block parallel processing during forward propagation, and the similarity-based result matrix and the gradients of the query Q, the key K and the value V are recalculated by using a recalculation strategy during back propagation. Compared with the prior art, the method has the advantages of reducing the overhead of attention calculation memory access, improving the operation efficiency and the like.

The invention discloses a multi-dimensional information-based adaptive gateway traffic scheduling method, which comprises the following steps of: acquiring server performance indexes, network delay, bandwidth and geographic position data in real time, and establishing a historical database; performance load weights are generated through weighted calculation of CPU, memory and disk indexes, and routing priorities are dynamically adjusted by adopting exponential function mapping; performing normalization processing on network bandwidth, delay and geographic distance, and calculating a service access weight to optimize a transmission path in combination with a step function; analyzing historical traffic data based on an LSTM model to predict a future trend, and generating a traffic prediction weight through a sigmoid function to realize pre-equalization; and combining the three types of weights, weighting to generate dynamic routing configuration, eliminating abnormal nodes in real time in combination with a health check mechanism, triggering high-load early warning and linking a predictive balancing strategy. According to the method, multi-dimensional index collaborative decision-making is realized, routing distribution is dynamically optimized, network delay is effectively reduced, and system throughput and stability in a high-concurrency scene are improved.

A system and method are provided for placing network functions among respective locations in a network. The locations at which the network functions are placed can be nodes and network devices within the network. These nodes can be selected, e.g., based on which network devices have available capacity and or specialized hardware (e.g., accelerator sin a data processing units (DPUs)) that is optimized for particular network functions. The network functions can include an inline network function that is provisioned directly in a data plane of one of the network devices (e.g., in-lined directly in a hardware offload device without a virtual machine and without a container). The decision of where to place the network functions can be based on a performance metric (e.g., representing available computational / memory resources at the network nodes) and / or a network-function metric (e.g., representing consumed computational / memory resources by the network functions) to improve system performance.

The invention relates to a quick expansion method based on run length coding, which comprises the following steps of: S1, taking a binary image as an input region and carrying out run length coding to obtain a run length; inputting expansion parameter height and width; s2, judging whether the height and width of the expansion parameters are less than or equal to 0; s3, judging whether the input area is rectangular or not; s4, calculating the number of possible maximum distribution runs, wherein the maximum run number is obtained by multiplying the run number of the input area by the input expansion height; s5, calculating the number of times required to be iterated; s6, executing expansion in the horizontal direction; s7, expansion in the vertical direction is executed; and S8, merging all the moved run length codes. According to the method, the run length coding technology is introduced, the algorithm execution process and the data representation mode are optimized, the defects and problems existing in the prior art are solved from the aspects of storage, calculation, internal storage, real-time performance and the like, the efficiency and performance of binary image expansion operation are improved, and important technical progress is brought to the field of image processing.

Aspects of the disclosure are directed to a tree-based network architecture for serving and / or training machine learning models. The architecture includes one or more multi-chip packages having a plurality of compute-memory stacks connected via an input / output (I / O) die. The I / O die includes an aggregator to aggregate computations from the compute-memory stacks. The architecture can further include a plurality of the multi-chip packages connected on a server via a server level aggregator and a plurality of the servers connected on a rack via a rack level aggregator for further aggregation of the computations from the compute-memory stacks. The tree-based network architecture allows for fewer hops, resulting in lower latency and savings in bandwidth when serving and / or training machine learning models.

The invention relates to the technical field of edge computing resource management, in particular to an edge server load evaluation method based on analytic hierarchy process and performance loss. According to the method, firstly, edge servers are divided into a common type, a computing type, a memory type and an I / O type according to heterogeneous types; aiming at each type of edge server, constructing a judgment matrix by adopting an analytic hierarchy process and solving a feature vector so as to calculate load weight coefficients of CPU (Central Processing Unit), memory and disk I / O (Input / Output) resources; calculating a real-time load based on the weight coefficient, wherein the real-time load is the weighted sum of the resource utilization rates; the performance loss is further calculated according to the nonlinear relation between the real-time load and the total load ratio; and finally, restraining the real-time load through the load threshold value, and evaluating the performance state of the server in combination with the performance loss. According to the method, the accuracy and reliability of load evaluation of the heterogeneous edge server are effectively improved, the resource utilization rate is optimized, overload of the server is avoided, and the system stability is enhanced.

The invention discloses a high-concurrency virtual service transfer scheduling method and system based on a cloud edge collaborative architecture, and relates to the technical field of cloud computing and edge computing collaboration, and the method comprises the steps: constructing a service gene analysis model at an edge node, responding to a virtual service access request, extracting the resource consumption characteristics of a service flow in real time, and calculating a service separation potential energy index. The virtual business is dynamically decoupled into a connection anchoring phase and a computing power free phase based on the index; establishing a load inertia monitoring mechanism, modeling resource consumption of edge nodes into a kinematics system, collecting speed and acceleration of load change in real time, calculating system pressure momentum, and generating a graded unloading instruction when the momentum exceeds a preset critical collapse threshold value; starting a convergent differential injection mechanism, pre-constructing a logic shadow at a cloud end, and calculating a convergence ratio of a memory dirty page generation rate to a network transmission rate in real time; the method has the advantages of being high in practicability, having the pre-judgment capacity and being capable of achieving lossless switching.

The invention belongs to the technical field of semiconductors, and particularly relates to a dual-mode computing memory controller and a memory system for a PIM-DRAM. The dual-mode computing memory controller used for the PIM-DRAM comprises an address conversion module used for processing address mapping between a host and a PIM core; the command translation module is used for converting the host command into a PIM operation instruction; the command generation module is used for generating an address mapping command; the data translation module is used for managing data streams among the DDR bus, the on-chip bus and the DRAM; the multi-mode state machine is used for dynamically switching to a memory mode or a PIM mode according to different memory commands sent by the host; and the dual-mode computing access module is used for selecting an access space of the DRAM according to the address mapping command or the data route. According to the method, efficient and low-delay PIM operation is achieved by dynamically switching the memory and the calculation mode, meanwhile, the method is compatible with a traditional DDR protocol and can be directly integrated to an existing system, and a host interface does not need to be modified.

The invention discloses a heterogeneous BIM model lightweight server intelligent scheduling method and system. The method comprises the steps that a data storage structure is constructed, and an engine information table, a server information table and a task information table are designed; according to the engine identification code, obtaining unit task memory consumption and server memory configuration information from the engine information table and the server information table, counting the total number of server tasks and the number of lightweight task success from the task information table, calculating a lightweight success rate, and counting the number of tasks in processing from the cache structure; based on the unit task memory consumption, the server memory configuration, the lightweight success rate and the number of tasks in processing, calculating a memory usage amount, a memory occupancy rate and a residual computing power, and determining a weight factor according to the lightweight success rate to obtain a weighted residual computing power; and realizing server scheduling based on the calculated memory occupancy rate and weighted residual computing power. By adopting the method, model resource consumption and server residual computing power can be dynamically matched, and the average utilization rate of a cluster memory is improved.

Dynamic provisioning of resources in a datacenter improves the utilization efficiency of compute, memory, storage, and network resources, while maintaining flexibility to meet changing demands. Embodiments herein disclose protocol-aware provisioning of resources over Compute Express Link (CXL) fabrics, enabling multi-protocol pooling and disaggregation of resources, including memory and workload-specific accelerators such as GPUs and DSAs. In some embodiments, a Resource Provisioning Unit (RPU) facilitates intent-based protocol translations and mappings between address spaces, potentially enabling the creation of large-scale compute-memory fabrics that may utilize both coherent and non-coherent Non-Transparent Bridging (NTB) between multiple protocols in a single system, serving as the underlying infrastructure for executing workloads such as Large-Language Models (LLMs) and Deep Learning Recommendation Models (DLRMs). Some embodiments also optimize low-latency communication between processes running on different nodes by enabling host-to-host memory provisioning for libraries such as OpenMP, Pthreads, or CUDA, which can utilize shared memory.

The invention discloses a cache capacity control method, device, equipment and system, relates to the technical field of computers, and can improve the utilization rate of memory resources. The method can be applied to a cluster, the cluster comprises a scheduler management node and a plurality of computing nodes, the method is executed by the scheduler management node, and the method comprises the following steps: the scheduler management node receives a cache resource request sent by a first computing node, and allocates a cache resource to the first computing node according to the cache resource request and a resource allocation strategy; determining a target resource quantity allocated to a cache system of the first computing node from a computing memory of the first computing node to obtain a resource allocation result; and sending the resource allocation result to the first computing node. Wherein the resource allocation result is used for indicating that a target resource quantity in idle resources of the computing memory is divided into the cache system, and the resource allocation strategy comprises at least one of the following items: an occupation parameter of the computing memory, an occupation parameter of the cache system and a reserved resource quantity of the computing memory.

An apparatus, system and method for an object-recognizing retail purchase system. The apparatus, system and method may include an automatically adjustable camera rig comprising a plurality of movable cameras, wherein the plurality of movable cameras are automatically moved by a camera control platform according to characteristics of an object within a view field of the plurality of movable cameras; a first input for receiving images from the automatically adjustable camera rig; and a second input for receiving a plurality of scraped network images regarding a plurality of purchasable objects. Additionally included may be a first computing memory for storing an object profile for each of the plurality of purchasable objects, wherein each of the object profiles comprises at least data from the first input regarding the object within the field of view and data from the second input; and a purchasing platform at least partially present on a mobile device.

A Fully Analog STate-Space Compute-In-Memory (FAST-CIM) architecture implements cascaded CIM arrays that maintain continuous analog signal flow throughout neural network computations. Sequential data patches are processed through cascaded CIM arrays, where a feedforward CIM array performs initial vector-matrix multiplication using analog computations within memory cells, and the analog output flows directly through a gain circuit to a recurrent CIM array without digital conversion. The gain circuit converts analog current signals to voltage signals, enabling direct analog connection between the cascaded arrays. The recurrent CIM array executes State-Space Model (SSM) computations, processing the cascaded analog signals along with previous state information maintained by a State Write and Propagate (SWAP) circuit that stores states using capacitive elements. The cascaded array configuration eliminates analog-to-digital and digital-to-analog converters between processing stages, achieving reduced power consumption and latency compared to conventional implementations that require digital interfaces between CIM arrays.

The present application is applicable to the field of data loading technology and provides a data loading method, apparatus, computer equipment, and storage medium, wherein the method comprises: obtaining a first target storage capacity required for loading target data from a disk in a terminal into a memory; obtaining the remaining computational storage capacity of the memory, and when it is determined that the remaining computational storage capacity is less than the first target storage capacity, calculating the ratio of the sum of the used computational storage capacity of the memory and the first target storage capacity to the actual total available amount of the memory to obtain a calculation result; based on the calculation result, when it is determined that the terminal is in a target operating state, loading the target data into the memory. This solution can reduce the frequency of heating of electronic devices, increase the service life of electronic devices, and enhance the user experience.

A predictive analytics apparatus, engine, system and method capable of providing real time analytics in a manufacturing system that may include a data input capable of receiving raw data output from at least one machine operable to effect the manufacturing system embodiments, and a processor to execute code from a computing memory. The code may comprise an adaptor to push the received raw data to a database to processed data; an extractor to extract the processed data from the database; predictive analytics to receive the extracted processed data and apply thereto a predictive model comprised of target data for the at least one machine, and to provide feedback to the at least one machine to modify performance of the at least one machine based on the application of the predictive model; and a visualizer capable to provide at least a visualization of the feedback and the performance.