35results about How to "Improve capacitance effect" patented technology

A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode. Furthermore, a multi-rate etching process may be used to etch the top electrode and insulator layer of an MIM structure, using a first, higher rate to perform an anisotropic etch up to a point proximate an interface between the conductive and dielectric materials respectively defining the top electrode and insulator layer of the MIM structure, and then using a second, lower rate to perform an anisotropic etch to a point proximate an etch stop layer defined on the bottom electrode of the MIM structure.

A manual device comprising a longitudinal prehension body and a pad for a capacitive screen mounted on one end of said body, wherein the body is insulating, while the pad is conductive, and a rod of polymer material filled with at least one conductive material and / or comprising a conductive coating is electrically in contact with the pad and extends longitudinally inside the body.

A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

An electrical receptacle connector includes an insulated housing, upper-row receptacle terminals, and lower-row receptacle terminals. The insulated housing includes a base portion and a tongue portion extended from one side of the base portion. The tongue portion has an upper surface, a lower surface, and a front lateral surface. The lower-row receptacle terminals correspond to the upper-row receptacle terminals and include signal terminals which include high speed transmitting terminals. Each of the high speed transmitting terminals includes a bending portion, an extension portion, and a cutout portion. The bending portion is extended upward from the front end of the flat contact portion and inserted into the tongue portion, the extension portion is extended forward from the top of the bending portion toward the front lateral surface, and the cutout portion is defined at the extension portion and near to the bending portion.

The invention discloses a pixel structure and a display panel. The pixel structure comprises an active component, a share switch component, a protective layer, a color filtering pattern, a pixel electrode, a share capacitor and a shading material. The protective layer covers the active component and the share switch component; the color filtering pattern with an opening is disposed on the protective layer; the pixel electrode is disposed on the color filtering pattern; the share capacitor is electrically connected with the share switch component and comprises an electrode wire, an insulating layer covering the electrode wire and an electrode pattern; the electrode pattern is disposed on the insulating layer and thus generates a first capacitive coupling effect with the electrode wire; the protective layer covers the electrode pattern and is exposed through the opening; the pixel electrode extends to the opening for generating a second capacitive coupling effect with the electrode pattern; and the shading material covers the pixel electrode extending to the inside of the opening.

The invention discloses a left-handed material based on a cavel-shaped basic unit structure, and relates to the left-handed material. The left-handed material is provided with a dielectric substrate; the upper surface of the dielectric substrate is covered with a metal good conductor layer; the cavel-shaped basic unit structure consists of two symmetrical circular arc-shaped recursive helical structures etched in the two sides of a midperpendicular of the good conductor layer and a linear metal rod in the center and connected therewith; and the midpoint of the bottom edge of the metal rod coincides with the center of the dielectric substrate. The circular arc-shaped recursive helical structure is obtained by connection of multiple sections of circular arcs in a tangential manner in sequence based on radiuses from big to small and field angles of certain sizes; and an included angle is formed between the tangent line on the starting point of the helical structure and the metal rod. The cavel-shaped structure of the good conductor layer is copied into n parts, and is rotated for 360 degree / n by taking the midpoint of the bottom edge of the metal rod as the centre of a circle to be placed, so that the petal-shaped left-handed material can be further formed.

The present invention proposes a method for manufacturing a graphene electrode resonator, comprising: 1) in a tube furnace, the resonator is placed in a quartz tube, and an inert gas is charged to remove the air in the quartz tube; 2) heating Keep at 1000-1200° C. for 30-60 minutes; 3) At the end of the reaction, cool the system to room temperature under inert gas. The present invention also proposes a graphene electrode resonator, comprising: a resonator quartz shell layer and a resonator graphene electrode layer, and the resonator graphene electrode layer is attached to the inner side of the resonator quartz shell layer. The graphene-coated resonator proposed by the invention has high electrical conductivity, good capacitance effect, large charge storage, high exchange efficiency, and can reduce the drive voltage of the resonator.

An electrical connector comprises an insulative housing, a plurality of terminals and a plurality of wires. The plurality of terminals are fixed to the insulative housing, each terminal has a fixed portion fixed to the insulative housing and a contact portion and a soldering portion which are respectively connected to the fixed portion, the soldering portion of each terminal of at least a part of the plurality of terminals is formed with a bending section, and an inner surface of the bending section defines a filling space for filling a solder. A plurality of wires are respectively soldered to the soldering portions of the plurality of terminals and make the solder filled in each filling space.

The invention discloses a liquid crystal display panel and a production method thereof. The liquid crystal display panel comprises a pixel array. The pixel array comprises a plurality of data lines, a first insulating layer, a plurality of scanning lines, a plurality of active elements, a plurality of capacitive electrodes, a second insulating layer and a plurality of pixel electrodes. The first insulating layer covers the data lines and is provided with a plurality of grid holes and a plurality of source holes. The scanning lines are formed on the first insulating layer. Each active element comprises a grid, a source and a drain. The sources, the grids and the capacitive electrodes are formed on the first insulating layer. The second insulating layer covers the capacitive electrodes, the sources and the drains. The pixel elements correspond to the capacitive electrodes and are formed on the second insulating layer. The scanning lines are electrically connected with the corresponding grids via the corresponding grid holes, and the data lines are electrically connected with the corresponding sources via the corresponding source holes.

The invention discloses a preparation method for iron-doped bismuth tungstate. The method comprises the following steps: bismuth nitrate pentahydrate is added to a citric acid-containing aqueous solution to form a metal-citrate complex; after 10 minutes of vigorous stirring, sodium tungstate dehydrate and sodium bicarbonate are added to the above solution; after further stirring for 5 minutes, thefilling degree in a reactor is 50%, the heat is preserved for 15 h under the temperature of 180 DEG C, and cooling to room temperature is carried out; the taken reactant is centrifugally cleaned withalcohol and distilled water three times each, and a flower-like bismuth tungstate material is obtained; DMF and distilled water with a volume ratio of 8 to 2 are measured and mixed as a mixed solvent; the above bismuth tungstate and ferrous chloride tetrahydrate are added to the mixed solvent; after further stirring for 5 minutes, the filling degree in the reactor is 50%, the heat is preserved for 2 h under the temperature of 100 DEG C, and cooling to room temperature is carried out; the taken reactant is centrifugally cleaned with alcohol and distilled water three times each, and an iron-doped bismuth tungstate material is obtained.