72results about How to "Improve operating profit" patented technology

A ferromagnetic film according to the present invention includes ferromagnetic element and nonmagnetic element and has a first portion and a second portion. Concentration of the nonmagnetic element in the first portion is lower than an average concentration of the nonmagnetic element in the ferromagnetic film. On the other hand, concentration of the nonmagnetic element in the second portion is higher than the average concentration of the nonmagnetic element in the ferromagnetic film. The nonmagnetic element includes at least one element selected from the group consisting of Zr, Ti, Nb, Ta, Hf, Mo and W. The ferromagnetic film is applied to a magnetic free layer of a magneto-resistance element in an MRAM.

A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.

A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.

In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.

In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

To make it possible to appropriately set a capturing timing for a pixel value.

For this, the present invention includes a pixel array unit 2 composed of pixels 21 arranged in a row direction and a column direction in a matrix manner and a latch unit 62 provided for each column constituting the pixel array unit 2 and configured to convert a pixel value of the pixel 21 into a digital pixel value to hold the pixel value. Also, the present invention includes a column scanning unit 4 for selecting the latch unit 62, a capturing unit 9 for sequentially capturing the pixel value held by the latch unit selected by the column scanning unit 4 in synchronism with a predetermined clock, and a delay unit 10 for delaying a clock for driving the capturing unit 9 in a plurality of stages. With the configuration described above, first dummy data is set in the latch unit 62-m at the near end, and second dummy data is set in the latch unit 62-0 at the far end. Then, a delay amount in the delay unit 10 is set as a delay amount at which both the first dummy data and the second dummy data can be captured by the capturing unit 9.

A semiconductor memory device includes first and second global bit lines; first, second, third and fourth local bit lines; first, second, third and fourth hierarchical switches for respectively connecting the first global bit line and the first local bit line to each other, the second global bit line and the second local bit line to each other, the first global bit line and the third local bit line to each other, and the second global bit line and the fourth local bit line to each other; and first and second precharge circuits for respectively precharging the first and second global bit lines. When a memory cell connected to the first local bit line is read, the third hierarchical switch is turned off, and the first precharge circuit terminates its precharge operation after the third hierarchical switch is turned off and before a selected word line connected to the memory cell to be read is activated.

Systems and methods for controlling fluid flow utilizing a synthetic jet actuator, are provided. An example of a synthetic jet actuator system includes a synthetic jet actuator including a dual bimorph subsystem to provide low, medium, and high synthetic jet velocities and/or fine flow control response, and an arc-forming subsystem to provide enhanced pressure, velocity, and mass flow performance, enhanced flow control response, and/or heating of the fluid within the bimorph chamber to extend the performance or operating margin of the dual bimorph subsystem of the synthetic jet actuator. The arc-forming subsystem includes a pair of electrodes interfaced with inner surface walls of the dual bimorph subsystem. Various configurations of power supplies can be utilized to provide simultaneous function to both the subsystem and the arc-forming subsystem to allow selective activation.

A driving method of a stacked light modulating device for recording an image therein, which includes selective reflection layers each having a cholesteric liquid crystal, reflecting light with different wavelengths within a visible range, and being different in a lower threshold value of texture change from a planar to a focal conic texture with respect to an externally applied voltage and an upper threshold value of texture change from the focal conic to a homeotropic texture, and a pair of electrodes disposed outside, includes applying between the pair of electrodes voltages including a voltage V1 and have a same frequency, to select an area exceeding or not exceeding the upper threshold value in each of the selective reflection layers, and applying voltages including a voltage V2 and have a same frequency different from the voltage V1, to select an area exceeding or not exceeding the lower threshold value.

An interlace-type PDP is driven by an improved driving method so as to achieve a greater operating margin, higher resolution, and higher brightness. The interlace-type PDP is driven using odd and even frames in such a manner that the cells are grouped into cell groups such that each cell group includes two or three cells which are adjacent in a direction crossing the electrode pairs, and the cells are driven in units of cell groups. The grouping of cells is performed differently for even and odd frames such that, in one type of frame, locations of two or three cells grouped into each group are shifted by one cell, in the direction crossing the electrode pairs, from the locations of cells grouped together in the other type of frame.

The invention provides an electronic shelf advertising system capable of being controlled wirelessly and timely. The system comprises an advertising information server and more than one electronic shelf advertising device, wherein the advertising information server is connected with wireless transceivers, and is used for carrying out unified management on the advertisement information and promotion of commodities; and the electronic shelf advertising devices are respectively arranged on each shelf or in stores, and are used for receiving and broadcasting commodity advertising information and promotion information sent by the advertising information server, each electronic shelf advertising device comprises a display screen and a wireless transceiver, and the display screen is connected with the wireless transceiver. According to the invention, static or dynamic advertisements can be made at commodity display parts or in stores, thereby increasing the purchasing desire of consumers, and increasing the revenues and profits of merchants.

The invention discloses an intelligent equipment management cloud service system which comprises a data acquisition module, a data aggregation and transmission module, a database module, an application center management service module, a cloud service business application module, a network module, a user access module and a firewall module. The data acquisition module and the data aggregation and transmission module are connected via the network module, and the cloud service business application module and the user access module are connected via the network module; the data aggregation and transmission module, the database module, the application center management service module and the cloud service business application module are in data connection with each other; the firewall module is in through connection with the data aggregation and transmission module, the database module, the application center management service module, the cloud service business application module, the network module and the user access module. The intelligent equipment management cloud service system is characterized by capability of allowing enterprises to choose leases according to demand of service items, convenience of use, reduction of expenditure and cost of the enterprises, and improvement of business operation profits.

The invention discloses a multifunctional buckle assembly automatic system which comprises a first rack and a conveying sliding table mechanism. A buckle mechanical arm and a buckle feeding mechanismare mounted in the first rack. A first conveying belt is arranged on the upper end face of the first rack. A vertical conveying mechanism is arranged beside the first conveying belt. One end of the conveying sliding table mechanism stretches into the first rack, and the other end of the conveying sliding table mechanism is located outside the first rack. At least one rotary disc is arranged at theaction tail end of the buckle mechanical arm, and multiple buckle clamps are arranged on the surface of the outer circle of the rotary disc. According to the multifunctional buckle assembly automaticsystem, through the arrangement of the conveying sliding table mechanism, the buckle mechanical arm, the buckle feeding mechanism, the first conveying belt and the vertical conveying mechanism, the functions of automatic product feeding, buckle assembly and the like are combined, and lean production novelty is achieved; and by means of the multifunctional buckle assembly automatic system, the efficiency is improved, the cost is reduced, enterprise lean production management is facilitated, intelligent factories are achieved, and earned profits are improved.

A static random access memory comprises a pre-charge unit that supplies a pre-charge voltage to first and second bit lines connected to a bit cell; a capacitor, of which one or the other terminal is selectively connected to a ground terminal; a clamping unit that selectively connects the bit lines with the capacitor to adjust a voltage level of the bit lines; and a mux unit that is included in a unit memory cell including the bit cell, the pre-charge unit, the capacitor and the clamping unit, and activates the bit lines of the unit memory cell in response to reception of a selection signal; wherein the clamping unit connects the first and second bit lines with the capacitor in response to a charge sharing control signal, to induce charge sharing between the first and second bit lines and the capacitor.