2results about How to "Reduce verification workload" patented technology

The application discloses a kind of for EFlash BIST function verification method, comprising the following steps: S1, in register transfer level (RTL) top layer instantiation an EFlash BIST sequence generation module, waiting for chip power-on reset to enter working state, the test mode control pin of general input and output interface of chip is set high, and chip enters test mode;S2, generate excitation sequence through EFlash BIST sequence generation module and input excitation sequence to BIST interface through general input and output interface, after BIST controller converts excitation sequence into access operation to FLASH module, execute current operation and return operation result data to EFlash BIST sequence generation module to carry out next round operation.The application can ensure the correctness and reliability of BIST controller function and part FLASH particle function, improve the overall verification efficiency of chip.

The present application belongs to the technical field of information security, and particularly relates to a multi-seal stamping system based on a block chain smart contract. The present application realizes the cooperation of multiple units and multiple seals, initiatively adds a multi-seal approval mode on the platform side, covers the blank of such a scene in the market, and realizes that units that join the platform can join the seal approval flow; the present application proposes a set of localized or platformized seal verification logic based on a smart contract relying on specific hardware equipment, and does not need to rely on a verification code to perform manual verification on a webpage, thereby truly reducing the verification workload and realizing that the device can only be automatically verified locally before being started.