57results about How to "Reduce loop area" patented technology

One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

A flexible printed circuit improves data transfer rates by disposing ground wires in a ground plane proximate to signal wires disposed in a signal channel plane. One or more ground wires is associated with each signal wire pair or each signal wire for imaging of the return currents of the signal pairs. An overlapping alignment minimizes loop area between a ground wire and its associated signal wire. An offset alignment provides a reduced loop area and reduced breakage risk since movement of the flexible-circuit does result in compression of the signal wire and its associated ground wire. A combination of overlapping and offset alignment balances signal transfer effectiveness with breakage risk by offsetting ground and signal wires is stress sensitive regions and overlapping ground and signal wires in stress tolerant regions. In one embodiment, the flexible circuit interfaces a portable computer with a display lid to support high-speed display signals with reduced breakage risk from cycling the display lid between an open and closed position.

According to a semiconductor device (101), a first switching active element (103) of a normally-on type and a second switching active element (104) of a normally-off type are cascode-connected to each other. This causes an electric current path to be formed. The first and second switching active elements (103, 104) are provided and connected so that loop area of the electric current path is a minimum area in a plan view of the semiconductor device (101).

An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1). A third foil element may be installed to electrically interconnect the discrete second device surfaces (B). The foil elements reduce interconnection parasitics and reduce charge and thermal energy density at device conductive surfaces as compared to wire bonded electrical interconnections. The foil elements may be comprised of formed metal elements that are flexible but sufficiently rigid to hold a formed shape or flexible foils supported on a flexible dielectric substrate.

An electrical assembly (300, 400) includes a power IC such as a MOSFET (112, 412) attached to a substrate module (114, 214). The MOSFET includes a top surface comprising first and second conductive device surfaces (A, B), associated with first and second device ports, and a bottom surface comprising a third conductive device surface C associated with a third device port. A first foil element is bonded to the first conductive device surface(s) A and to each of the first conductive substrate surfaces (A1, A2) and provides a continuous conductive pathway from each conductive surface (A) to each other conductive surface (A) and to each conductive surface (A1, A2). A second foil element is bonded to the second conductive device surface(s) B and to the second conductive substrate surface B1 and provides a continuous conductive pathway from each device conductive surface (B) to the substrate conductive surface (B1). A third foil element may be installed to electrically interconnect the discrete second device surfaces (B). The foil elements reduce interconnection parasitics and reduce charge and thermal energy density at device conductive surfaces as compared to wire bonded electrical interconnections. The foil elements may be comprised of formed metal elements that are flexible but sufficiently rigid to hold a formed shape or flexible foils supported on a flexible dielectric substrate.