67 results about "Electric-field screening" patented technology

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

The invention relates to a semiconductor device. The semiconductor device comprises a semiconductor material layer; a gate trench and a gate structure, the gate trench extending from the top surface of the semiconductor material layer into the semiconductor material layer; the gate structure is located in the gate trench; the source electrode regions are positioned between the adjacent grid electrode grooves; the source region comprises a well region and a source contact region located above the well region; the anti-punch-through structure is located in the well region, and the doping concentration of the anti-punch-through structure is larger than that of the well region; the first electric field shielding structures are located between the adjacent grid electrode grooves; wherein the depth of the first electric field shielding structure is greater than that of the gate trench. According to the invention, the anti-punch-through structure and the first electric field shielding structure with relatively high doping concentration are arranged, so that the blocking voltage bearing capability of the device under a short channel condition can be remarkably improved, the gate oxide reliability is improved, and the stability and reliability of the device in long-term working can be further improved.

The application relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stack. A second step and a third step are formed on the side of the conductive channel film away from the second insulating layer; the second step and the third step are arranged along the stacking direction. A first contact electrode is formed on the second step surface through oblique angle deposition, and a second contact electrode is formed on the third step surface through oblique angle deposition; the side surface of the first contact electrode facing the third step is aligned with the end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited through the oblique angle deposition mode, the dependence on a photoetching device and a overlay process precision in the development process of the existing field effect transistor is reduced, and the channel length and the gate length are simultaneously micronized.

The present application belongs to the technical field of semiconductors. Disclosed are a silicon carbide power device cell structure and a preparation method therefor, and a semiconductor device. A silicon carbide power device comprises a substrate, source structures, a gate structure, and electric-field shielding structures, wherein the gate structure is disposed in the substrate; the source structures are disposed on the substrate and surround at least part of side faces of the gate structure; and the electric-field shielding structures are disposed in the substrate, surround the bottom of the gate structure and are connected to the source structures. The present application can redistribute to the electric-field shielding structures an electric field of a gate dielectric layer of a silicon carbide semiconductor device cell structure in a reverse blocking state, so as to maximize the shielding effect, thereby reducing the electric field of the gate dielectric layer, such that the semiconductor device has high reliability.

The present application relates to the technical field of material mechanical property testing, and proposes an electric field device for testing fiber filament lift, which is used to solve the key problem that the lift characteristics of fiber materials cannot be accurately measured in a dynamic electric field environment in the prior art, and promote its application in aerospace protection, bionic driving and intelligent material design. The device provides a stable and adjustable electric field environment through a modular electric field generating system, provides the electric field force source necessary for the fiber filament to generate lift; the electric field intensity in the electric field generating system is measured by redundantly arranging electric field sensors; the external electromagnetic interference is isolated and the internal electric field is constrained by the electric field shielding shell to prevent leakage, and at the same time, the internal components are protected from dust and debris. Through the collaborative design of the modular electric field generating system, the self-adaptive lifting system and the high-sensitivity sensing technology, the present application realizes the accurate simulation and real-time measurement of the typical electric field of Mars atmosphere (0-20kV / m).

The invention discloses a semi-conductive paper-wrapped aluminum cable paper tape structure and an oil-immersed composite voltage transformer, and the structure comprises an inner layer which is disposed at one side of a base layer and is used for uniformizing the distribution of an electric field; the base layer is used for arranging the inner layer and the outer layer; and the outer layer is arranged on the other side of the base layer and is used for structural shaping and electric field shielding. The base layer is used as a base layer for arranging the inner layer and the outer layer, needs to be made of an insulating material (such as cable paper), has certain mechanical strength and can be made into a composite material with the inner layer and the outer layer on the basis of ensuring insulation, the inner layer is used for uniformizing an electric field, and the outer layer forms a Faraday cage to improve the shielding performance and also has certain mechanical strength. In addition, a structure shaping effect is also needed, so that the shielding layer can be made into a plate-shaped shielding layer, and can also be made into a shielding tube as shown in Figure 7.

The application discloses a kind of electric field shielded rotary friction and wear testing machine, comprising: rotary drive device, can drive ring sample mounting rod positive and negative rotation;Ring sample mounting rod, ring sample can be installed;Vertical loading device, can drive block sample mounting table lifting, so that the block sample on block sample mounting table and the ring sample on ring sample mounting rod abut to exert loading force, and adjust the size of loading force;Detection device, between vertical loading device and block sample mounting table, including loading force sensor and two opposite friction force sensors, loading force sensor is used to detect vertical loading force, the axial direction of ring sample mounting rod, the force direction of loading force sensor and friction force sensor is perpendicular;Block sample mounting table, can install block sample;Electric field shielding box, above rack, block sample mounting table and ring sample mounting rod are located in electric field shielding box. To provide a kind of can simultaneously meet the test demand of rotary friction pair and swing friction pair friction and wear testing machine.

The application discloses a display panel and a display device, relates to the technical field of display, and further relates to an array substrate, a color film substrate, an electric field shielding layer, a shielding electric field insulating layer and a data line arrangement layer. The color film substrate is not provided with a black matrix corresponding to the data line on the side of the array substrate. The electric field shielding layer comprises a plurality of shielding electrodes. The orthographic projection of each shielding electrode on the substrate covers the orthographic projection of each data line on the array substrate body. The shielding electric field insulating layer comprises a first insulating part, a second insulating part and a third insulating part which are sequentially connected. The second insulating part is arranged corresponding to the shielding electrode. The thickness of the second insulating part is greater than the thickness of the first insulating part and the thickness of the third insulating part. The application reduces the pressure difference and improves the transmittance through the above design.

The adjustable high-voltage polar plate array device comprises an insulating barrier plate and a plurality of high-voltage polar plates which are sequentially arranged at intervals in the front-back direction, the insulating barrier plate comprises a bottom plate, a left side plate and a right side plate, the left side plate and the right side plate extend from the bottom plate to the same side, and conductive sliding grooves extending in the front-back direction are fixedly formed in the left side plate and the right side plate respectively; the left end and the right end of the high-voltage polar plate extend into the conductive sliding grooves respectively, and the left end and the right end of the high-voltage polar plate are in sliding connection with the conductive sliding grooves respectively. According to the invention, the high-voltage polar plate is directly inserted and fixed in the conductive chute in the insulating barrier plate, the assembly structure is simple, the contact is tight, the stable formation of an electric field is facilitated, and meanwhile, a good electric field shielding effect and relatively high safety are achieved; the distance between the high-voltage polar plates can be adjusted according to the particle sizes and physiological characteristics of different forage grass seeds, so that the seeds are subjected to uniform and stable electric field action in the treatment process, and the reliability and consistency of the treatment effect are improved.

The invention relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stacked mode. A second step and a third step are formed on one side, far away from the second insulating layer, of the conductive channel film; the second step and the third step are arranged in the stacking direction. Forming a first contact electrode on the second step surface through oblique angle deposition, and forming a second contact electrode on the third step surface through oblique angle deposition; one side surface of the first contact electrode facing the third step is aligned with one end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited in an oblique angle deposition mode, the dependence on photoetching equipment and overlay process precision in the development process of an existing field effect transistor is reduced, and synchronous miniaturization of the channel length and the grid electrode length is achieved.

The embodiment of the present application provides a trench MOSFET device, a manufacturing method and a chip, the device comprises a first cross section area, a second cross section area and a third cross section area which are arranged alternately along a first direction; the first cross section area, the second cross section area and the third cross section area all comprise: an N-type substrate, an epitaxial layer, a first trench, an oxide layer, a first N area, a P well area, an N+ area, a second trench, a gate and a source; the epitaxial layer is arranged on one side of the N-type substrate; the first N area is arranged below both sides of the first trench; the N+ area is arranged on both sides of the first trench; the P well area is connected below the N+ area; the second trench is arranged at the bottom of the first trench; the P area at the bottom and the corner of the second trench of the first cross section area and the P area at the bottom of the first trench of the third cross section area play an electric field shielding role, so that the device damage caused by the strong electric field at the corner of the trench is avoided, and the reliability of the device is improved.

This application provides a wafer cleaning method, belonging to the field of semiconductor technology. The wafer cleaning method includes: providing a wafer, the wafer including a first region and a second region; forming a plurality of piezoelectric structures on the first region of the wafer, the piezoelectric structures including sequentially stacked electric field shielding layers and piezoelectric layers; performing a semiconductor manufacturing process to form a semiconductor structure on the second region, after forming the semiconductor structure, the surface of the wafer has carbon-containing organic matter; performing a two-fluid cleaning process on the surface of the wafer, the piezoelectric structures causing the generation of oxide groups during the two-fluid cleaning process, and using the oxide groups to remove the carbon-containing organic matter on the surface of the wafer. This application can efficiently and safely remove carbon-containing organic matter from wafers.

A spacing-assured gas discharge tube assembly is installed on a printed circuit board, which may be part of a motor controller. The discharge tube assembly includes a tube body and an electrostatic spacing shield disposed at least partially around the tube body. The shield is configured to prevent close physical proximity of adjacent structures having electrostatic fields that may alter the breakdown voltage of the tube body.

The invention discloses a double-line-belt laser-electrolysis composite milling machining system which comprises a workpiece, a circulation and power system, a double-line-belt laser beam system and a composite milling cutter head. The laser beam system forms focusing line band laser with adjustable spacing and length through a beam splitter, a reflection cavity and a shaper, and the composite milling cutter head realizes uniform injection of electrolyte and shielding of an electric field through an electrode core with an array micro-flow groove, a conductive grid mesh and a suction device with a flexible insulating wall. The temperature of a machining area is increased through laser thermal activation, the electrochemical reaction activity is enhanced by cooperating with the electrolysis effect, the reaction area is limited through the insulating wall, a boundary electric field is shielded, and a multi-energy-field coupling mechanism is formed. Double-line-band laser can expand energy field coverage, and the machining efficiency and the surface quality are improved by combining electrolyte laminar flow and electric field uniformization design; the non-contact combined machining avoids deformation of large thin-wall components, and is suitable for high-quality and high-efficiency machining of large-format components in the fields of aerospace and the like.

The application provides a power VDMOS device with anti-single particle effect gate damage, which comprises a first conductive type substrate, an epitaxial layer and a high concentration doped source, a second conductive type buried layer, a well region and a high doped region. A gate dielectric, a gate electrode, a passivation layer and a source metal electrode are formed above the first conductive type epitaxial layer. The second conductive type buried layer is located directly below the gate, covers the whole JFET region and part of the second conductive type well region, and the longitudinal distance between the second conductive type buried layer and the second conductive type well region is greater than half of the JFET width defined by the distance between two adjacent second conductive type well regions. The structure utilizes the electric field shielding and carrier conduction effect of the buried layer, can significantly inhibit the gate degradation caused by irradiation without sacrificing the JFET resistance, and can also reduce the Miller capacitance and improve the high frequency characteristics of the device.

The invention relates to a transformer and a manufacturing method thereof, and belongs to the technical field of electrical equipment, and the transformer comprises a coil winding which comprises a winding part and a wire outlet part, and the wire outlet part is connected with the winding part; the coil winding is mounted on the coil framework; the first electric field shielding layer is configured to shield the whole of the coil framework and the coil winding; the main insulating layer coats the outer side of the first electric field shielding layer, and the wire outlet part extends out of the main insulating layer; the second electric field shielding layer wraps at least part of the periphery of the main insulating layer; the coil framework comprises a supporting part and an extension part, the winding part is installed on the supporting part, one end of the extension part is connected with the supporting part, and the other end of the extension part extends out of the main insulating layer along the wire outlet part. The main insulating layer between the first electric field shielding layer and the second electric field shielding layer is uniformly distributed and is not layered, so that the risk of breakdown caused by over-high local field intensity of the main insulating layer is effectively reduced, and the insulation reliability of the transformer is improved.

To provide a high-voltage detection device for powder spray that is capable of detecting high voltage of multiple discharge wires arranged in close proximity within a confined place serving as a powder spraying closed space.SOLUTION: A high-voltage detection device 10 for powder spray comprises: detection means 40 which includes a spraying unit that has a powder storage tank, a spraying roller, and discharge wires and a scattering-prevention unit that is arranged immediately below the spraying unit, forms a spraying closed space between rollers, and has two scattering-prevention rollers arranged with a gap relative to a spraying target and forcibly rotated and discharge wires, and which detects high voltage applied to the discharge wires of the powder spray; and signal processing means 50 which is connected to the detection means, and determines a live-wire state of the discharge wires. The detection means faces the discharge wires, and surrounds portions other than a detection surface of a detection electrode having a length equal to a diameter of the discharge wire with an electric field shielding part. The signal processing means sets a gain that can be detected at a close distance from the discharge wires in an amplification part.SELECTED DRAWING: Figure 1

The application belongs to the technical field of semiconductor devices, and provides a high-surge multi-stage trench Schottky diode and a preparation method thereof. The Schottky diode comprises an anode, an epitaxial wafer and a cathode arranged in sequence. The epitaxial wafer comprises a semiconductor substrate and an epitaxial layer. The epitaxial layer is provided with a plurality of deep trenches on a side in contact with the anode; each deep trench comprises n sub-trenches, the width of each sub-trench gradually decreases in a direction pointing to the bottom along the opening of the deep trench, and n is a positive integer greater than 1. The inner wall and the bottom of each deep trench are provided with a hetero-barrier layer, and a field plate dielectric is further provided in contact with the hetero-barrier layer; and the opening of the deep trench is surrounded by the hetero-barrier layer. The deep trench is filled with a filling structure. The high-surge multi-stage trench Schottky diode has a better electric field shielding effect in a reverse blocking state, can further reduce the electric field of the metal-semiconductor interface, and improve the breakdown voltage of the device, the surge capacity and the long-term working reliability.

The present invention discloses an electrostatic shielding structure for a liquid crystal display (LCD), comprising a transparent conductive film coated on the front side of a conductive glass substrate of the LCD; the transparent conductive film is connected to a common reference ground of a circuit board of the LCD via a grounding lead. The LCD electrostatic shielding structure of the present invention coats the front side of the conductive glass substrate of the LCD with the transparent conductive film. The transparent conductor's electric field shielding effect shields the electrostatic field generated by static charges on the display surface, thereby protecting the liquid crystal layer of the LCD from the effects of the electrostatic field. This allows the LCD to function normally in environments with sustained high electrostatic voltages without sacrificing optical performance or electrical reliability, while maintaining a flexible mechanical design.

A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.

The invention provides a current sensor without a magnetic core. The current sensor comprises an inverted cylindrical magnetic shielding body, an electric field shielding body, a diversion body, a magnetic field gradient sensing module and a signal processing module. By optimizing the structural design of the current conductor, the magnetic field gradient in the sensing direction of the magnetic field gradient sensing module by the current flowing through the current conductor is constructed or increased. And meanwhile, the magnetic shielding body and the electric field shielding structure which are arranged in a nested manner are utilized to form a three-dimensional anti-electromagnetic interference capability, so that the measurement precision, the working stability and the reliability of the current sensor are further improved. The current sensor provided by the invention has the advantages of small size, simple process, wide measuring range, high measurement precision, high frequency response and the like by laminating, nesting and assembling related parts under the condition of no magnetic core, and can well adapt to the special requirements of a future current precision measurement scene on the miniaturization and high frequency response of the current sensor.

The application belongs to the technical field of semiconductor device preparation, and relates to a metal mesh source electrode for a transistor, a transistor, a preparation method of the transistor and application of the transistor. In view of the problems of serious gate electric field shielding of a source electrode, discontinuous conductive path, difficult control of geometric morphology, and insufficient current injection uniformity and stability in the prior art, the application provides a metal mesh source electrode for a transistor, which comprises a metal conductive layer with mutually interconnected metal stripes and forming a grid gap, the stripe width of the metal stripes is 0.2-20 microns, and the duty cycle is 10-50%. The application further provides a preparation method of the metal mesh source electrode, which forms a crack template on the surface of a substrate and deposits metal, and removes the crack template to obtain a metal mesh conductive layer with controllable structure. Meanwhile, the application further provides application of the metal mesh source electrode in a vertical field effect transistor.

The invention relates to the technical field of semiconductors, and discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor substrate layer; an epitaxial layer located on the semiconductor substrate layer; the electric field shielding region and the doped region are located in the epitaxial layer, the doped region is located on the side, away from the semiconductor substrate layer, of the electric field shielding region, and the doped region is exposed out of the surface of the side, away from the semiconductor substrate layer, of the epitaxial layer; the metal layer is located on the surface, deviating from the semiconductor substrate layer, of the epitaxial layer, and at least part of an opposite region between the metal layer and the electric field shielding region does not coincide with the doped region; and the electric field shielding region and the doped region have the same conduction type and are opposite to the conduction type of the epitaxial layer. The reverse voltage withstanding characteristic of the semiconductor structure is improved, and the reverse electric leakage characteristic is reduced.

The invention relates to a super junction semiconductor structure and a preparation method thereof, and the structure comprises a first conductive type substrate, a plurality of first conductive type first epitaxial layers, a first conductive type attraction region, and a first conductive type second epitaxial layer. Second conduction type ions are injected into the first conduction type first epitaxial layers to form second conduction type first column regions, each row of second conduction type first column regions are connected to form second conduction type first columns, and the first conduction type attraction regions are arranged in the second conduction type first columns; the first conductive type second epitaxial layer is provided with a first groove, the first groove is filled with a second conductive type material to form a second conductive type second column, and the second conductive type second column is connected with the corresponding second conductive type first column. And a relatively large electric field shielding area is formed, so that EAS avalanche is optimized, and the reliability of the device is improved.

The embodiments of the present application relate to a trench gate transistor, comprising: a semiconductor material layer; a gate trench comprising a side wall and a bottom wall, wherein the side wall comprises at least two first portions spaced apart in an extending direction and second portions located between adjacent first portions; first electric-field shielding structures located outside the gate trench and adjacent to the first portions; a body region located outside the gate trench and adjacent to the second portions, wherein the portion of the body region near the gate trench is used for forming channel regions; a drift region located below the channel regions; and second electric-field shielding structures located below the first electric-field shielding structures and having at least a portion extending below the channel regions, such that in the extending direction, the width of the drift region located between adjacent second electric-field shielding structures is smaller than the width of the channel regions. In this way, the saturation current of a device is significantly reduced, and the short-circuit performance of the device is optimized, thereby achieving a good balance among specific on-resistance (Rsp), a protection effect, and short-circuit performance.

The invention relates to a load switch for a switch cabinet and the switch cabinet. The load switch includes: a bracket; the three-position switch comprises a first static contact and a grounding static contact which are fixedly arranged on the bracket; the first moving contact is rotatably arranged on the support, and the first moving contact is provided with a closing position jointed with the first static contact, a grounding position jointed with the grounding static contact, and an isolation position between the first static contact and the grounding static contact; the vacuum arc-extinguishing chamber is connected with the three-position switch in parallel and comprises a shell, a second static contact and a second moving contact which are arranged in the shell, and the second moving contact is connected with a moving conductive rod extending out of the shell; and the first shielding piece is arranged near the shell in a manner of equipotential with the movable conducting rod, and the first shielding piece is provided with an opening for the second movable contact to pass through so as to provide electric field shielding during the switching-on and switching-off period.

The application belongs to the technical field of semiconductor manufacturing, and provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a shielding gate, a gate, a body region, an injection region and a deep buried layer. The epitaxial layer is located on the front surface of the substrate. A plurality of grooves are arranged in the epitaxial layer. The shielding gate and the gate are arranged at intervals and located in the grooves. The body region is located on the side of the epitaxial layer away from the substrate. The injection region is located on the side of the body region away from the epitaxial layer. The deep buried layer is located in the epitaxial layer and on the opposite sides of the grooves along a first direction. By introducing the deep buried layer, a depleted electric field shielding layer can be formed on both sides below the grooves, thereby avoiding the concentration of the electric field in the weak areas such as the bottom of the grooves, reducing the high peak electric field around the shielding gate, making the electric field distribution in the device more uniform, and improving the breakdown voltage of the device.

An integrated multipole connector (1) comprising: a socket housing (11) in which a first conductor unit (12) with a shielding contact (123) for electric field shielding and a second conductor unit (13) with a shielding cover (133) for electric field shielding are mounted, wherein the second conductor unit (13) has a different current capacity than the first conductor unit (12), a plug housing (21) connected to the socket housing (11), in which a first plug connection (23) electrically connected to the first line unit (12) and a second plug connection (24) electrically connected to the second line unit (13) are mounted in the plug housing (21), a connector shielding sleeve (22) arranged in the connector housing (21) to shield the electric fields of the first and second connector terminals (23, 24), and a socket shielding sleeve (14) arranged in the socket housing (11) to shield an electric field between the socket housing (11) and the plug housing (21) by connecting with the plug shielding sleeve (22) when the socket housing (11) is connected to the plug housing (21).

The invention provides an electromagnetic compatibility high-frequency prediction method based on an improved LSTM, and relates to the technical field of high-frequency prediction methods, and the method comprises the following steps: building a metal shielding box example model; a metal shielding box equivalent circuit is constructed based on a Robinson algorithm, and the shielding effectiveness is solved; and obtaining data of the shielding effectiveness of a plurality of electric fields, and predicting the shielding effectiveness of the metal box body by using a CNN-BiLSTM-AdaBoost method. Compared with traditional LSTM, the model is higher in accuracy when being applied to shielding effectiveness prediction of the metal cavity.

The invention relates to the technical field of high-voltage direct-current transmission equipment monitoring, and discloses a high-voltage direct-current converter valve cooling system pressure sensor lifting device and method.The method includes the steps that a gradient stress ring and an electric field shielding cover are arranged, and the fringe effect is restrained from the physical level; after field installation, pre-pressurizing processing is carried out to optimize a pressure conduction path, and a two-step data compensation algorithm is adopted: an original digital signal is corrected by using a nonlinear edge effect compensation model established based on a maximum deviation feature point; a precise pressure value is calculated through a linear basic relation model, a compensation coefficient self-adaptive updating mechanism is further included, through periodic field calibration, coefficients of an edge effect compensation model are only pertinently updated when the measurement deviation exceeds the limit, and therefore precise compensation is conducted on long-term drift on the premise that the basic characteristics of the sensor are not changed. According to the invention, physical suppression is combined with an adaptive algorithm, so that the full-period service measurement repeatability and environmental adaptability of the sensor are improved.