A
thin film transistor display panel includes gate wiring formed on an insulation substrate and including gate lines,
and gate electrodes
and gate pads connected to the gate lines; a gate
insulation layer covering the gate wiring; a
semiconductor pattern formed over the gate
insulation layer; data wiring formed over the gate
insulation layer or the
semiconductor pattern and including source electrodes, drain electrodes, and data pads; a
protection layer including a Nega-PR type of organic insulating layer formed all over the
semiconductor pattern and the data wiring, wherein the thickness of the Nega-PR type of organic insulating layer in both the gate and data pad regions is smaller than in the other regions; and a pixel
electrode connected to the drain
electrode. When exposing the Nega-PR type of
passivation layer in the pad region during a
photolithography process, a
photomask having a lattice pattern made of a
metal such as Cr that has a
line width of less than the resolution of a light exposer is used. Thus, the resulting post-etch height of the
passivation layer can be selectively controlled so as to provide reduced effective thickness in the pad regions.