3results about How to "Improve alignment tolerance" patented technology

This invention discloses a method for optical interconnection of silicon photonic chips based on meniscus-guided additive manufacturing, belonging to the field of silicon photonic chips. The method includes: in a controlled gas environment, using a printing material system containing polymers and organic solvents, stretching a liquid bridge between the optical interfaces of two silicon photonic chips using microneedles, and guiding the movement of the meniscus to form a polymer filament connecting the two ends. Subsequently, the solvent evaporates and solidifies, ultimately forming a free-space polymer optical waveguide spanning the chips. This method does not rely on high-energy lasers or adhesive application and washing processes, and is simple, low-cost, and highly efficient. The fabricated waveguides can achieve controllable spans from hundreds of nanometers to hundreds of micrometers in diameter and tens of micrometers to millimeters in length. The end faces can be optimized into controllable transition structures, effectively improving mode matching and coupling efficiency. It features low insertion loss, high alignment tolerance, and good mechanical stability, making it suitable for high-density silicon photonic packaging and heterogeneous integration.

The invention discloses a transistor, a preparation method thereof, a semiconductor device and electronic equipment. The transistor includes a channel, a gate structure, a first pole assembly, and a second pole assembly. The gate structure includes a gate electrode. The first pole assembly and the second pole assembly are located on the two sides of the gate structure in the first direction respectively and connected with the channel. The orthographic projection of at least one of the first pole assembly and the second pole assembly on the substrate is overlapped with the orthographic projection of the channel on the first plane; or, the orthographic projection of the first pole assembly and the orthographic projection of the second pole assembly on the first plane are not overlapped with the orthographic projection of the channel on the first plane, and the two ends of the gate structure in the first direction are correspondingly flush with the two ends of the channel in the first direction. According to the transistor and the preparation method thereof, the semiconductor device and the electronic equipment, the distance between the gate electrode and the source / drain electrode can be reduced, and the electrical property of the transistor can be improved.

The application discloses a dynamic electric connection mechanism, an electroplating device and a method. The dynamic electric connection mechanism comprises a fixed base assembly, a moving slide assembly driven by a cam driving assembly to move linearly back and forth, and a dynamic conductive path composed of conductive slides, the conductive slides keep sliding contact with static power supply terminals on the fixed base assembly in the whole moving process, thereby establishing a continuous and stable electric connection between the moving component and the power supply. The moving slide assembly is provided with the conductive slides on opposite sides respectively, forming parallel redundant current paths, which greatly improve the reliability and fault tolerance of the connection. The mechanism is applied to the electroplating device, drives the carrier hanger serving as a cathode to move back and forth and synchronously supplies power, and in combination with symmetrical spraying, can effectively remove bubbles in the holes of workpieces, ensure uniform current distribution, and significantly improve the uniformity and quality of the plating layer of semiconductor TGV deep hole electroplating.