30results about How to "Improve ladder coverage" patented technology

The invention provides an LED (Light Emitting Diode) chip provided with a stepped current blocking structure and a fabricating method thereof. The fabricating method comprises the steps of: providing at least one LED epitaxial wafer comprising a substrate and a light emitting epitaxial structure on the LED epitaxial wafer; fabricating the stepped current blocking structure on the surface of the LED epitaxial wafer vertical to a region of a first electrode correspondingly prefabricated; and fabricating transparent conductive layers on the surfaces of the LED epitaxial wafer and the stepped current blocking structure, and then fabricating a first electrode, a second electrode and a protective layer correspondingly. According to the LED chip provided with a stepped current blocking structure and the fabricating method of the LED chip provided with the stepped current blocking structure provided by the invention, the gradient at the edge of the stepped current blocking structure is slowed so that the contact area of the transparent conductive layer and the stepped current blocking structure is increased, the situation that the transparent conductive layer (ITO) on the side wall (at the step) at the edge of the current blocking structure becomes thinner and even breaks can be avoided, the step covering capacity of the transparent conductive layer is improved, the current spreading capacity of the transparent conductive layer is further improved, the electro-optical conversion efficiency of the LED chip is increased, and the brightness of the LED chip is enhanced.

The invention provides a display system with a capacitive touch panel and a manufacturing method thereof. The display system with a capacitive touch panel comprises a substrate, an electrode circuit, a plurality of signal lines, a dielectric layer and an electrode bridging structure, wherein the electrode circuit is provided with a first electrode and a second electrode, the first electrode comprises a plurality of first conductive patterns, the second electrode comprises a plurality of second patterns, and the first conductive patterns are mutually electrically connected; the plurality of signal lines are formed on the substrate; the dielectric layer is formed on the electrode circuit and covers the electrode circuit; and in the invention, the electrode bridging structure with uniform thickness is formed on the dielectric layer by using a metal open repair technique, so that the second patterns are mutually electrically connected.

A flash memory unit forming method comprises the steps as follows: a substrate is provided; a liner oxidation layer and an etching stop layer are formed sequentially on the surface of the substrate; at least two active areas are included in the substrate, and the adjacent active areas are isolated by a shallow trench isolation structure; the etching stop layer and the liner oxidation layer on the surface of the substrate are sequentially removed; a tunneling oxidation layer is formed on the surface of the substrate by a chemical vapor deposition method; and the tunneling oxidation layer is subjected to later stage oxidizing annealing treatment. The flash memory unit forming method provided by the invention avoids the double-hump effect and the reverse narrow channel effect, and the flash memory unit is better in period durability.

A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering stepincludes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

The invention provides a semiconductor assembly and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a first sealing ring and a second sealing ring whichare separated from each other on a substrate; forming a protective layer on the substrate for covering the first sealing ring and the second sealing ring, wherein the portion, between the first sealing ring and the second sealing ring, of the protective layer is provided with a concave surface; removing the protective layer at the concave surface and a part of the protective layer on the first sealing ring, forming a gap wall on the side wall of the first sealing ring, and forming an opening in the protective layer, wherein the width of the opening is greater than that of the first sealing ring, and the opening enables the top surface of the first sealing ring and the clearance wall to be exposed.

The present invention provides a film forming method for controlling holocrystalline hemispheric granule in small size by a combination etching treatment. The film forming method of a film formed on surface of the treated object W comprises a host crystal formed on the surface of the treated object by film forming gas, the host crystal grows, the HSG film forming process one the surface of the HSG film formed by holocrystalline hemispheric granule is formed; a hemispherical grained (HSG) film is oxidized to form an oxidized layer at the surface part of the HSG film, and then the oxidized layer is etched to be removed. Thus, the film forming method controls the holocrystalline hemispheric granule in small size by a combination etching treatment.