53results about How to "Reduce Power Noise" patented technology

An integrated control circuit for a resonant power converter includes a minimum-frequency programming circuit connected a first resistor to program a minimum switching frequency of the power converter. A feedback circuit is coupled to a feedback terminal to receive a feedback signal for generating an adjustment signal. A maximum-frequency programming circuit connects a second resistor to determine a maximum switching frequency in response to the adjustment signal. An oscillator is coupled to the minimum-frequency programming circuit and the maximum-frequency programming circuit to generate an oscillation signal for determining the switching frequency of the power converter. A feed-forward circuit is connected to a feed-forward terminal to receive a feed-forward signal represents the input voltage of the power converter. The switching frequency is increased in response to decrease of the feedback signal, and the switching frequency is increased in response to the increase of the feed-forward signal.

A NAND EEPROM having a shielded bit line architecture reduces supply voltage and ground noise resulting from charging or discharging bit lines. The EEPROM has a PMOS pull-up transistor and an NMOS pull down transistor connected to a virtual power node. A control circuit for charging or discharging bit lines controls the gate voltage of the PMOS or NMOS transistor to limit peak current when charging or discharging bit lines via the virtual power node. In particular, the control circuit operates the PMOS or NMOS transistor in a non-saturation mode to limit current. One such control circuit creates a current mirror or applies a reference voltage to control gate voltages. A programming method sets up bit lines by pre-charging unselected bit lines via the PMOS pull-up transistor having controlled gate voltage while latches in the programming circuitry charge or discharge selected bit lines according to respective data bits being stored. Another bit line setup includes two stages. A first stage pre-charges all bit lines via PMOS pull-up, and the second stage uses the latches to discharge or leave charged the selected bit lines depending on respective data bits being stored. The gate voltages of NMOS transistors in the programming circuitry can be controlled to reduce noise caused by discharging selected bit lines through the latches.

A stack package includes a first semiconductor chip first pads and second pads disposed thereon and a second semiconductor chip having third pads and fourth pads electrically connected with the second pads disposed thereon. Capacitors are interposed between the first semiconductor chip and the second semiconductor chip, and include first electrodes electrically connected with the first pads to of the first semiconductor chip, second electrodes electrically connected with the third pads of the second semiconductor chip, and dielectrics interposed between the first electrodes and the second electrodes.

An output circuit including: a tri-state output circuit capable of outputting high-impedance state, high-level state, and low-level state, in which the high-level state and low-level state are low-impedance state, and switching the high-impedance state and the low-impedance state in accordance with a first control signal; and a delay circuit outputting the first control signal to the tri-state output circuit by inputting a second control signal and delaying the second control signal so that timing delay time of the second control signal switching the high-impedance state to the low-impedance state is longer than the timing delay time of the second control signal switching the low-impedance state to the high-impedance state, is provided.

A semiconductor memory apparatus includes a bit line sense amplifier unit and a driving voltage supply unit. The bit line sense amplifier unit senses and amplifies a signal provided from a memory cell using a pull-up driving voltage provided through a pull-up power line and a pull-down driving voltage provided through a pull-down power line. The driving voltage supply unit supplies the pull-down driving voltage having a first pull-down driving force during a first amplification period, and supplies the pull-down driving voltage having a second pull-down driving force greater than the first pull-down driving force during a second amplification period after the first amplification period.

A data output device and method is disclosed, the device having a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal which is enabled or disabled according to the number of bits of the first output data having made level transitions, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal which is enabled or disabled according to the number of bits of the second output data having made level transitions, first and second logic units for performing logic operations with respect to pre-flag signals and data inversion flag signals, a first repeater for inverting or non-inverting and outputting a plurality of bits contained in the first output data in response to the first data inversion flag signal, and a second repeater for inverting or non-inverting and outputting a plurality of bits contained in the second output data in response to the second data inversion flag signal.

A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

The invention provides a mainboard with an integrated flash memory storage unit. The mainboard comprises a memory control module, an input/output control module, and an integrated flash memory storage unit which is integrated on the mainboard for storing data, a flash memory controller which is connected with the integrated flash memory storage unit, receives commands of the input/output control module and controls the communication of the integrated flash memory storage unit, and a direct memory access controller which cooperates with the flash memory controller in the control of the communication of the integrated flash memory storage unit. The mainboard with flash memory storage provided by the invention makes use of the advantages of quick reading and writing speed, good shock resistance and low power consumption of flash memory and uses the flash memory as a storage medium to form a storage unit of a computer, and the direct integration of the flash memory on the mainboard simplifies a circuit and reduces the volume and weight of the mainboard. According to the characteristics of the flash memory, the flash memory storage unit has a higher speed, lower energy consumption and noise as well as better safety compared with hard disk.

A semiconductor memory device includes an internal clock generator configured to generate an internal clock signal having a first clock period in response to a chip enable signal and change the first clock period of the internal clock signal in response to a clock control signal, and a controller configured to receive external commands including the chip enable signal and generate the clock control signal corresponding to a first external command other than the chip enable signal. Here, the semiconductor memory device performs a data input/output operation in response to the internal clock signal with the changed clock period.

The invention relates to the technical field of automatic carrying equipment, and particularly discloses an industrial intelligent motion control carrying robot. The robot comprises a motion chassis, a carrying plate is arranged on the motion chassis, an electric rotating disc is arranged between the motion chassis and the carrying plate, a carrying fork is arranged on one side of the upper portion of the carrying plate, automatic lifting of the carrying fork is achieved through a lifting power driving structure, an electric control box is arranged on the other side of the upper portion of the carrying plate and comprises a control system and a sensor system, a rotatable mechanical shaft arm structure is arranged between the carrying fork and the electric control box, a rotatable telescopic mechanical arm is arranged at the top end of the mechanical shaft arm structure, a rotatable mechanical gripper structure is arranged at the top end of the telescopic mechanical arm, and the mechanical gripper structure comprises a movable and turnable gripping plate. The high-low-position automatic carrying requirement is met, automatic loading and unloading are achieved in the whole process, and the overall automation degree is high.

The invention relates to a defectivity-immune technique of implementing MIM-based decoupling capacitors. An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.

The invention discloses a dust removal method and device for a ground horizontal well of a coal mine roadway driving face. The method comprises the steps that firstly, the ground horizontal well is reversely designed along a to-be-driven roadway; secondly, directional drilling of the ground horizontal well is conducted on a coal seam, and an easily-cut hole protection screen pipe is put into a horizontal section of the ground horizontal well and provided with holes; thirdly, water is injected into the ground horizontal well from the ground in a pressurized mode, and the water is injected into the coal seam through the holes of the hole protection screen pipe; and finally, coal mine roadway driving face driving is conducted, and when the driving face reaches the tail end of the horizontal section, a dust removal system arranged on the ground is started to pump and discharge dust generated by the driving face. According to the dust removal method and device for the ground horizontal well of the coal mine roadway driving face, the problems that the dust causes safety production of the driving face and worsens the working environment are solved, power noise is reduced, the construction efficiency of the driving face is improved, the health of underground constructors is protected, and the requirements for comprehensive dust prevention, safety, economy, energy conservation and environmental protection of the driving face are met.

A printed circuit board (PCB) includes at least one power trace. A plurality of etched portions are defined in the at least one power trace, acting as electromagnetic bandgaps for transferring resonant frequencies produced around the at least one power trace to avoid working frequencies of the PCB, thereby reducing power noise around the at least one power trace.

A power amplifier including a delta-sigma modulation module, a differential programmable dead-time-control module, and an output stage module is provided. The delta-sigma modulation module integrates and quantizes an error between a differential-mode input signal and an output signal to generate a first and a second mean signal. The differential programmable dead-time-control module includes a first and a second dead-time-control module which respectively generate a first and a second signal corresponding to the first mean signal and a third and a fourth signals corresponding to the second mean signal through logic calculations. The differential programmable dead-time-control module determines a dead time between the first signal and the second signal according to a first control signal and a dead time between the third signal and the fourth signal according to a second control signal. The output stage module generates the output signal according to the first, second, third, and fourth signal.

An image sensor including a first pixel circuit, a second pixel circuit, a first readout line, a second readout line, a first readout circuit, a second readout circuit and an average switch is provided. The first and second pixel circuits are in two columns of a pixel array. The first readout line transmits pixel data of the first pixel circuit to the first readout circuit. The second readout line transmits pixel data of the second pixel circuit to the second readout circuit. The average switch is arranged between the first and second readout lines and used to electrically connect the first and second readout lines in an average mode to average the pixel data on the first and second readout lines.

An air compressor device comprises a sound insulation shell, an air compressor, a condenser and an air storage tank. The air compressor, the condenser and the air storage tank are positioned in the sound insulation shell, the sound insulation shell is basically a rectangular solid and comprises a front panel, a rear panel, a left side plate, a right side plate, a top plate and a bottom plate which are connected together through bolts, a central partition is arranged at the center of the sound insulation shell, the middle area of the sound insulation shell is divided into two spaces by the central partition, the air compressor is mounted on the space of one side, the condenser and the air storage tank are mounted on the space of the other side, an air inlet channel is formed in one side of the sound insulation shell and positioned between the rear panel and an adjacent plate of the inner side of the sound insulation shell, an inlet of the air inlet channel is formed in the bottom plate, a plurality of air inlets are formed in the adjacent plate in a penetrating manner, and at least one air inlet is aligned to a compression portion of the air compressor.