12results about "Circuit masks" patented technology

A method for producing an electronic component comprises steps of providing a carrier in which conductor tracks and a contact structure are arranged on an upper side of the carrier, removing part of the material of the carrier on the upper side of the carrier in order to create a cavity with a recessed upper side in an environment of the contact structure such that the contact structure is raised above the recessed upper side, arranging a semiconductor chip above the contact structure, and establishing an electrically conductive connection between the contact structure and the semiconductor chip.

Reusable composite stencils for spray processes, particularly for spray processes used in the fabrication of integrated circuit devices, may be fabricated having a permanent core and at least one sacrificial material layer. Thus, in operation, when a predetermined amount of the sacrificial material layer has been ablated away by a material being sprayed in the spray process, the remaining sacrificial material layer may be removed and reapplied to its original thickness. Therefore, the permanent core, which is usually expensive and / or difficult to fabricate, may be repeatedly reused.

The application discloses a kind of FCBGA pattern exposure processes, comprising: step A: on circuit board, drill through hole;Step B: resin hole machine is used to resin hole to form resin hole to through hole with resin plug hole, wherein, resin hole inside contains resin material for protecting through hole;Step C: determine cutting area on the jig identical with the shape of circuit board, cutting area is carried out to cutting area, wherein, cutting area is the area corresponding to jig and resin hole;Step D: the jig is placed on the surface of thickening layer, and the thickening layer is cut along the edge of jig, so that the shape of thickening layer is identical with the shape of jig;Step E: the thickening layer is covered on the surface of circuit board, and the surface of circuit board forms exposed area not covered by thickening layer, and resin hole is located in exposed area;Step F: resin hole is used as the positioning hole of LDI exposure, and the circuit board after being attached to thickening layer is subjected to LDI exposure, and the application can improve the accuracy of LDI alignment, and improve production efficiency.

The invention relates to a method for manufacturing an interconnection level comprising a metallic line (62) and a metallic via (61), comprising: • forming, on a substrate (S), a first dielectric layer (21), • forming, on the first dielectric layer (21), a structured etching stop layer (30) comprising a first line pattern (301) and a via opening (30v), • forming, on the etching stop layer, a second dielectric layer (22), • forming, on the second dielectric layer (22), a second mask (40) defining a second line pattern (401) aligned with the first line pattern (301), • etching the second and first dielectric layers (22, 21), configured to form upper and lower cavities (50sup, 50inf) respectively, • filling the lower and upper cavities (50inf, 50sup) to form the metallic line (62) and the metallic via (61).

The invention provides a photosensitive resin composition, a photosensitive element, a method for forming a resist pattern, and a method for manufacturing a printed wiring board. The photosensitive resin composition according to the present invention contains a binder polymer, a photopolymerizable compound, and a photopolymerization initiator, and in the photosensitive resin composition, the binder polymer contains a structural unit derived from a (meth) acrylate compound having a dicyclopentyl group, and the weight molecular weight of the binder polymer is 7500-23000.

The present disclosure is titled "Printed Circuit Board Trace for Reducing Janning Effect." Apparatuses and methods for reducing etching within a printed circuit board due to the Janning effect are described, which can be used, for example, in a data storage device, such as a card-type data storage device. Specifically, a contact trace is coupled to a contact finger, which has a substantially greater surface area than the contact trace and is configured to couple the data storage device to a host device. The contact trace is electrically isolated from the rest of the circuit during the manufacturing process. The contact finger and an exposed portion of the contact trace are plated with a common material to reduce Janning etching of the contact trace during manufacturing. The contact trace is then connected to an impedance trace by at least one of a component and a bond wire.

A method for manufacturing an interconnecting level includes providing a substrate having a connecting terminal, forming a first dielectric layer on the substrate, and forming and structuring an etching stop layer on the first dielectric layer to define a first line pattern including a via opening. A second dielectric layer is formed on the etching stop layer, and a second mask defining a line pattern aligned with the first line pattern is formed. The dielectric layers are etched to form upper and lower cavities, which are filled with a metal material to form a metal line and a metal via connected to the connecting terminal.

The invention relates to a method for processing a bevel edge of a golden finger area of a printed circuit board, which sequentially comprises the following steps of: A, resistance welding and windowing: windowing a golden finger body and an adjacent lead area in a resistance welding process, and exposing a copper surface of the area; b, conducting wire area etching: completely removing the copper layer of the adjacent conducting wire area on the outer side of the golden finger body through a graphical etching process; and C, bevel edge forming: performing bevel edge cutting along the copper-free isolation strip formed by etching in the lead area, wherein the cutting boundary ends at the copper-free isolation strip and is far away from the golden finger body. The metal exposure risk during bevel edge cutting is thoroughly eliminated through the copper-free isolation strip, and an electrochemical migration path is blocked; no metal contact exists in the whole cutting process, conductive chippings are completely eradicated, and the hidden danger of short circuit in a high-frequency plugging scene is solved; the isolation belt design is compatible with conventional equipment precision, and the process error-tolerant rate and reliability are improved.

The invention belongs to the technical field of circuit board processing, and particularly relates to developing equipment and process for a circuit board, and the developing equipment comprises a rack, a conveying unit, a partition developing unit, an ultrasonic auxiliary unit, an online detection unit, a developing solution recycling unit, a temperature and pressure control unit and a central control system; the conveying unit, the partition developing unit, the ultrasonic auxiliary unit, the online detection unit, the developing solution recycling unit and the temperature and pressure control unit are all mounted on the rack and are electrically connected with the central control system; a'pre-developing-main developing-fine developing 'gradient parameter system is constructed through the partition developing unit, and is matched with a matrix type spray head capable of adjusting angles in a stepless manner, and the accurate matching of developing solution concentration, spraying pressure and ultrasonic energy is realized by combining the frequency dynamic adaptive design of the ultrasonic auxiliary unit.

A method for producing an electronic component comprises steps of: providing a carrier, in which conductor tracks and a contact structure are positioned on a top side of the carrier; removing part of the material of the carrier on the top side of the carrier in order to create a cavity with a recessed top side in a vicinity of the contact structure, such that the contact structure is raised above the recessed top side; positioning a semiconductor chip above the contact structure; and establishing an electrically conductive connection between the contact structure and the semiconductor chip.

An apparatus and method for manufacturing a power module is provided. The power module includes: a circuit board having a metal pattern formed thereon; a terminal coupled to the circuit board and electrically connected to at least a portion of the metal pattern; a power device chip bonded to the circuit board and electrically connected to at least a portion of the metal pattern and the terminal; and a molding part covering the power device chip and the circuit board. The circuit board includes: a base part comprising an insulating material; a pattern layer disposed on at least one of an upper surface and a lower surface of the base part and providing the metal pattern; and a thin film resistor having a predetermined circuit pattern connecting the metal patterns disposed on the base part to each other.

The embodiment of the application discloses a kind of inkjet printing method and the preparation method of PCB board, inkjet printing method includes: providing substrate;Inkjet printing phase change ink on the surface of substrate, form first graphic layer;Inkjet printing non-phase change ink on the side of first graphic layer away from substrate, form second graphic layer;Wherein, the inkjet printing area of non-phase change ink at least with the edge region of first graphic layer overlaps;First graphic layer combines second graphic layer and forms preset printing layer of layer. Reduce the cost of process technology, and improve the preparation efficiency, improve the smoothness of the edge of preset printing layer of layer simultaneously.