2results about How to "Does not affect thickness" patented technology

This application relates to the field of solar cells, and particularly to a solar cell and photovoltaic module. The solar cell includes: a substrate; a tunneling dielectric layer and a doped conductive layer located on the surface of the substrate, the tunneling dielectric layer being located between the doped conductive layer and the substrate, the doped conductive layer containing a dopant element, the dopant element being N-type or P-type, the doped conductive layer having a plurality of spaced-apart first heavily doped regions extending along a first direction, the doping concentration in the first heavily doped regions being greater than the doping concentration in the doped conductive layer excluding the first heavily doped regions; a passivation layer located on the surface of the doped conductive layer away from the substrate; and a plurality of spaced-apart electrodes extending along a second direction, the electrodes penetrating the passivation layer and contacting the doped conductive layer, with at least two first heavily doped regions contacting the same electrode. This application embodiment is beneficial for improving the photoelectric conversion efficiency of passivated contact solar cells.

This invention discloses a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, comprising: a semiconductor body, the semiconductor body including a well region, a first region, and a second region; the first region is disposed on a first surface of the semiconductor body, and the well region is disposed on the side of the first region away from the first surface; the first surface also has a gate trench; the gate trench includes a first gate sub-trench and a second gate sub-trench that are adjacent to and penetrate each other in a first direction; the extension depth of the first gate sub-trench in the thickness direction of the semiconductor body is greater than the extension depth of the second gate sub-trench in the thickness direction of the semiconductor body; a first insulating layer covers the inner walls of the first gate trench and the second gate trench; a gate is located in the gate trench on the side of the first insulating layer away from the second surface; a source is located on the first surface; and a drain is located on the second surface. This improves the stability of device performance.