3 results about "Silicon microstructures" patented technology

The application discloses a MEMS optical resonant accelerometer, and belongs to the field of micro-nano mechanical and electrical systems and optical sensing. The accelerometer comprises a glass base, a silicon microstructure layer, a safety structure group, a two-quadrant photodetector and a light source. The two-quadrant photodetector is arranged at the center of the glass base. The silicon microstructure layer is provided with a force-receiving base and a mass block connected through four groups of vertical force amplification units. The force-receiving base is provided with a folding beam type safety structure at four corners. The mass block is provided with a circular light transmission hole at the center and is coaxially aligned with the two-quadrant photodetector. Electrostatic comb drive groups are symmetrically arranged on both sides of the mass block to excite resonance. The light source emits a vertical light beam which is received by the two-quadrant photodetector through the light transmission hole. When acceleration acts on the force-receiving base, the inertial force is converted into axial stress of the mass block through a lever mechanism to modulate the resonant frequency. When the phase of the light intensity signal lags behind the driving signal by 90 degrees, the system is locked in the resonant state, and the acceleration is calculated through frequency offset to realize high-precision measurement of acceleration.

The invention provides a high-reliability electric signal vertical lead-out method of a vacuum sealing MEMS chip, which comprises the following steps: S1, carrying out metal layer or dielectric layer deposition, photoetching and etching on the bottom surface of a vertical lead layer of the MEMS chip to form a bonding pattern layer; wherein the vertical lead layer is a TGV layer or a TSV layer; s2, performing alignment eutectic bonding sealing packaging on the silicon wafer containing the silicon microstructure and the bonding pattern layer; wherein a sealing support sheet is arranged at the bottom of the silicon wafer; and S3, depositing a metal film layer on the top surface of the bonded vertical lead layer, and forming an electrode bonding pad through photoetching and wet etching, so that the electrode bonding pad is conducted with a silicon lead of the silicon wafer. A graphical bonding sealing process is combined with the TSV or the TGV containing the metallized filler with good conductivity, so that the air tightness process requirements of the metallized filled TGV and the TSV are favorably relaxed, and a process scheme which gives consideration to the high vacuum sealing performance of the MEMS chip and the high-reliability vertical extraction of an electric signal is provided.

The present disclosure relates to a method for at least one of forming a part or modifying a part, and a system therefor. The method involves initially providing a planar structure having a first material layer disposed on a second material layer. A lithographic operation including greyscale printing is performed to produce a resist material layer on the first material layer, with the resist material layer having a predetermined three-dimensional pattern extending along X, Y and Z axes, with features helping to define the three-dimensional pattern having differing dimensions along the Z axis, and which acts as a mask. An etch process is then performed, using the mask provided by the resist material layer, to etch the first material layer to impart the pattern of the mask as an etched pattern into the first material layer in accordance with a predetermined selectivity etching ratio, such that the etched pattern in the first material layer includes features formed with greater dimensions than corresponding features in the mask of the resist material layer.