37results about How to "Low state" patented technology

The present invention provides quantum cascade lasers and amplifier that operate in a frequency range of about 1 Terahertz to about 10 Terahertz. In one aspect, a quantum cascade laser of the invention includes a semiconductor heterostructure that provides a plurality of lasing modules connected in series. Each lasing module includes a plurality of quantum well structure that collectively generate at least an upper lasing state, a lower lasing state, and a relaxation state such that the upper and the lower lasing states are separated by an energy corresponding to an optical frequency in a range of about 1 to about 10 Terahertz. The lower lasing state is selectively depopulated via resonant LO-phonon scattering of electrons into the relaxation state.

A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.

The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation. The switching occurs in only one clock cycle.

When the worn state of the webbing is lifted, current of a current value I0 corresponding to the appropriate storing speed of the webbing is supplied to the motor, whereby a take-up shaft rotates and the webbing is taken up. At a point in time when the webbing has been taken up to the extent that the webbing does not hinder the exiting of a vehicle by a passenger, the size of the supply current to the motor is reduced from the initial current value I1 to a current value I1. A reference current value IL of a stall current for determining whether to stop the motor when a foreign object or the like has become entangled between the webbing and an in-vehicle part can also be set to be small in correspondence to the reduced current value I1.

In an exemplary embodiment, a sliding component includes an annular stationary side seal ring 5 fixed to the stationary side and an annular rotating side seal ring 3 to be rotated together with a rotating shaft, in which by relatively rotating opposing sealing faces S of the stationary side seal ring 5 and the rotating side seal ring 3, a silicate-containing sealed fluid present on one side in the radial direction of the relatively rotating sealing faces S is sealed, wherein an amorphous carbon film 8 formed by using a hydrocarbon gas containing no silicon compound is provided on at least any one of the sealing faces S of the stationary side seal ring 5 and the rotating side seal ring 3, and content of silicon of the amorphous carbon film 8 is 1.5 at % or less.

A driver circuit is provided for enabling a transistor collector-emitter path to be used as a broadband periodic switch. The broadband driver circuit controls the magnitude of the transistor base-emitter current in order to enable a CLOSED switch state and to simultaneously control the magnitude of the transistor base-emitter reverse-bias voltage in order to enable the OPEN-switch state. The precise control of these parameters minimizes base-charge storage and prevents reverse-breakdown failure.

The invention includes a design structure embodied in a computer readable medium for performing a method for inserting a scan chain into a VLSI circuit design. The scan chain structure, or structures, are included in the design structure for the VLSI circuit design. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain. Buffer circuit control elements control the first flip-flop (L1) to switch between scan mode or low power leakage mode. The switching occurs in only one clock cycle. The design structure can include a netlist, which describes the VLSI circuit, reside on storage medium as a data format used for the exchange of layout data of integrated circuits, and preferably includes at least one of test data files, characterization data, verification data, or design specifications.

An antenna module is provided. The antenna module comprises a first radiation conductor, a second radiation conductor, a short-circuit element (s / c element), a ground plane, a feed-in cable and a spurious radiation conductor. One terminal of the second radiation conductor is near the first radiation conductor with a gap. One terminal of the s / c element is connected to the second radiation conductor and the other side of the s / c element is connected to the ground plane. The feed-in cable comprises a centre conductor and an external conductor, wherein the centre conductor is connected to the first radiation conductor and the external conductor is connected to the ground plane. The spurious radiation conductor is connected to the second radiation conductor. The second radiation conductor comprises a spurious radiation plate, a first radiation piece and a second radiation piece within the two sides of the second radiation conductor. The first radiation piece and a second radiation piece are in parallel and a gap is conducted between the first radiation piece and the second radiation piece.

Semiconductor device circuits and methods are provided for adjusting core processor performance based on usage metrics. Metric detection and adjustment are performed in digital logic hardware guided by registers providing maximum and minimum frequency settings, without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Power-performance drivers provide applications or the operating system ability to specify maximum and minimum frequency requirements.

An oscillator circuit includes an amplifier including at least two terminals for receiving a crystal and an automatic amplitude control loop coupled to the amplifier including biasing circuitry switched between a first operational mode and a second operational mode. The first operational mode occurs during an initial time period and the second operational mode occurs after the initial time period is expired. The biasing circuitry includes first and second PMOS transistor circuits, each transistor circuit including an unswitched PMOS transistor and a switched PMOS transistor. Alternatively, the biasing circuitry can include first and second NMOS transistor circuits, each transistor circuit including an unswitched NMOS transistor and a switched NMOS transistor. The biasing circuitry is under control of an internally generated control signal.

A hollow aluminum structure that will be brazed includes at least one brazing sheet having a filler metal layer clad onto a core layer. The core layer is composed of aluminum or an aluminum alloy containing less than 0.2 mass % Mg. The filler metal layer is composed of an aluminum alloy that contains Si: 4.0-13.0 mass % and Bi: 0.01-0.3 mass %, and further contains Li: 0.004-0.08 mass % and / or Be: 0.006-0.12 mass %, the filler metal layer containing less than 0.1 mass % Mg. The hollow aluminum structure is assembled such that the filler metal layer is present at locations that will form both an interior-facing brazed joint and an exterior-facing brazed joint. Then, flux is applied onto the filler metal layer at the location that will form the exterior brazed joint, and the hollow aluminum structure heated in an inert gas atmosphere to form the interior brazed joint and the exterior brazed joint.

Even when temperature sensors (12, 13) used in a device for warming a battery (1) being not in use by using a battery-driven heater (2) have failed, the battery (1) is prevented from freezing. Based on a battery temperature (Tb) and an outside air temperature (Ta), times (Δt1 to Δt8) during which Tb will decrease down to a warming start temperature (Tb_start) are each set to the next controller startup time (Δt). A controller (9) is started up every Δt, at t2, t3, and t4, and checks whether Tb<Tb_start is satisfied or not. At t4 when Tb<Tb_start is satisfied, a heater (2) is battery-driven to warm the battery (1). After t0 when the outside air temperature sensor (13) fails, the outside air temperature (Ta) is set to a fixed value (Ta_const) and based on this Ta=Ta_const and the battery temperature (Tb), the above control is repeated. Accordingly, it is unlikely that the temperature information (Ta) from the outside air temperature sensor (13) that is at fault causes Δt to become extremely long like ∞, so that it is avoided that the heater (2) cannot be operated because the controller (9) cannot be started up and the battery (1) freezes.

The present invention is generally directed to a method of making chalcogenide glasses including holding the melt in a vertical furnace to promote homogenization and mixing; slow cooling the melt at less than 10° C. per minute; and sequentially quenching the melt from the top down in a controlled manner. Additionally, the present invention provides for the materials produced by such method. The present invention is also directed to a process for removing oxygen and hydrogen impurities from chalcogenide glass components using dynamic distillation.