80results about How to "Lower characteristic impedance" patented technology

The invention provides an inter-board perpendicular interconnection circuit structure for a substrate integrated ridge waveguide (SIRW), and aims to provide a millimeter wave inter-board perpendicular interconnection circuit structure with small volume, easy integration, high interconnection property and long-term reliability. The inter-board perpendicular interconnection circuit structure is implemented by the following technical scheme: the SIRW (3) perpendicular to the surface of a base board is integrated on an LTCC multilayered circuit board (1); a substrate integrated ridge waveguide opening is etched in a corresponding outlet in the metal ground on the surface of the LTCC multilayered circuit board (1); Z-direction metalized filling holes (2) are arranged to form a metal hole gate array to equivalently form the waveguide wall and single-side ridges in the waveguide; metallic shield holes and probe restraining cavities (7) on the two sides of a 50-ohm strip line (8) are arranged at the equal spacing; and the alignment pressing and connection of the SIRW interfaces on the opposite sides between two boards is realized through pin hole alignment, so that the perpendicular interconnection transition of the millimeter wave signal between two boards in a way of 50-ohm strip line-SIRW-SIRW-50-ohm strip line is realized consequently.

An insulating layer is formed on a support substrate having a conductive property. Write wiring traces, read wiring traces, and first and second electrode pad pairs are formed on the insulating layer. The first electrode pad pair is connected to the write wiring traces. The second electrode pad pair is connected to the read wiring traces. Parts of regions of the support substrate, which overlap the electrode pads, are removed. Thus, openings are formed in the regions of the support substrate, which overlap the electrode pads.

An electronic component and an electronic-component production method in which the magnitude of a stray capacitance produced between adjacent outer electrodes is controllable. The electronic component includes a chip body and first to fourth outer electrodes. In the chip body, first and second coil block are sandwiched between magnetic substrates. Dielectric layers are interposed between the outer electrodes and the chip body such as to be away from exposed portions of coil patterns in the coil blocks. The dielectric layers have a width larger than a width of the outer electrodes, and a dielectric constant of the dielectric layers is set to be lower than the dielectric constant of the magnetic substrates.

A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.

The invention relates to a microwave plasma exciter device comprising: a waveguide containing means (23) for concentrating the microwaves; and means (110, 120) for forming a plasma, which are disposed in a microwave concentration zone.

The invention provides a terahertz frequency multiplier with a multi-level lower waveguide matching structure, and belongs to the technical field of terahertz devices. The terahertz frequency multiplier is simple in structure and convenient to process; a plurality of lower waveguide matching structure sections are introduced to the input end and the output end of the multiplier to reduce the characteristic impedance of the waveguide, and therefore, a matching circuit of a probe circuit and a main circuit of the frequency multiplier can be simplified, and moreover, single-die transmission can be performed for an input signal through a main die and while some stray waves at the output end of the frequency multiplier can be inhibited.

Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential.

Disclosed herein is a rigid flexible PCB having openings. The rigid flexible PCB includes a flexible section with flexibility and rigid sections being formed at the edges of the flexible section with mechanical stiffness. The flexible section comprises a flexible plane. The flexible plane comprises a base insulating layer; a wire conducting layer being adhered to one of the top side and the bottom side of the base insulating layer; and a plane conducting layer adhered to the other of the top side and the bottom side of the base insulating layer. The plane conducting layer has a plurality of openings being formed as a mesh structure. According to the rigid flexible PCB of the invention, the flexibility of the flexible section and the characteristic impedance of signal wire traces may be improved.

An electronic device having a printed circuit board having a ground, an electrically insulating layer provided on a face of the printed circuit board, and an electromagnetic shielding layer adhered to the face of the printed circuit board through the electrically insulating layer. The ground of the printed circuit board and the electromagnetic shielding layer are conducted electrically.

A circuit substrate includes a first pair of ground lines, a second pair of ground lines, a plurality of first connection lines, a plurality of second connection lines and a plurality of conductive pillars. The first and second pairs of ground lines are located on first and second surfaces of the substrate, respecteively. The pillars are located in the substrate and vertically conducted between the first pair of ground lines and the second connection lines and between the second pair of ground lines and the first connection lines, and the first and second pairs of ground lines are conducted, so that a 3-D grounding circuit loop is formed. Moreover, a first pair of signal lines is disposed between the first connection lines for grounding and a second pair of signal lines is disposed between the second connection lines for grounding to get a better signal integrity.

A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulating layer, and a plurality of ground patterns in a stripe form are formed to be parallel to one another on the thin metal film. The wiring patterns and the ground patterns are provided in a staggered manner so that they are not opposed to one another with the base insulating layer interposed therebetween. In other words, the ground patterns are provided to be opposed to regions between the wiring patterns.

The invention discloses a design method of an ultra-wideband radio frequency power dividing feed network. The embedded design of the ultra-wideband radio frequency power dividing feed network is realized by combining a planar resistor embedding process with a microwave multilayer printed board manufacturing process. The characteristic impedance value of the strip line in the network is reduced through impedance conversion and power divider unit parameter optimization, the line width of the strip line in the feed network is widened under the condition that the thickness parameter of a printed board is not changed, and the circuit processing difficulty is effectively reduced. Through hole grid design is adopted around the power dividing feed network for electromagnetic shielding, signal crosstalk between circuits is reduced, and the electromagnetic compatibility of the circuits is effectively improved. On the basis of improving the integration level of the microwave circuit, the problem of interstage standing wave accumulation deterioration caused by cascade connection of the multi-stage power dividers is reduced; the increase of the line width of the internal network strip line reduces the influence of the processing error of the printed circuit on the radio frequency index of the circuit, and reduces the conductor loss of the feed network at the same time.

Contact terminals for grounding include a fixing portion for supporting an pressing portion of an actuator member, and contact terminals for signals disposed adjacent to the contact terminals for grounding include a fixing portion shorter than the fixing portion of the contact terminal for grounding. The fixing portion is connected to one end of a movable terminal portion.

The invention relates to an implement method for a plane micro-strip linear high-distribution ratio unequal power divider. Excessively high characteristic impedance is lowered by introducing the method of an improvement factor C, and a 'T'-shaped structure is used for replacing a quarter-wave transmission line with excessively low characteristic impedance, so that the line width of each microstrip line is in a reasonable range, and the difficulty in manufacturing the high-distribution ratio unequal power divider with a traditional plane microstrip line is solved. Moreover, compared with the prior art utilizing a double sided parallel strip line (DSPSL) or a non-ideal plane structure (DGS), the implement method has advantages in manufacturing cost and difficulty and circuit dimension.

The invention provides a method for generating dozens of megampere pulse currents and a z-pinch direct drive source. The drive source comprises a primary pulse power source (thousands of fast discharge branch circuits are connected in parallel), a high-voltage transmission cable, a water medium electromagnetic induction chamber, a secondary MITL (Magnetically Insulated Transmission Line) and a z-pinch load, wherein the secondary MITL is formed by connecting multi-stage induction chambers in series; the z-pinch load is located on an axis; thousands of primary discharge branch circuits are located at the peripheries of the induction chambers and are divided into dozens of groups; the primary discharge branch circuits discharge rapidly to directly obtain an electric pulse with a leading edge of 100-200 ns, a voltage of 100-200 kV and a current of 30-50 kA. Currents of the thousands of branch circuits are transmitted and gathered on cable interfaces, which are uniformly distributed at the peripheries of the induction chambers, of dozens of I-shaped tri-plate transmission lines through the cable; the currents are gathered to the induction chambers for primary excitation through the tri-plate transmission lines; and the current gathering is realized through electromagnetic induction. Multi-stage induction chambers are connected in series to form an IVA (Induction Voltage Adder); the MITL is employed for a secondary stage of the IVA to realize voltage superimposition and power transmission; an ultra-high power electric pulse with a voltage of dozens of MV, a current of dozens of MA and a leading edge of 100-200 ns is generated on the Z-pinch load of the axis, and the requirement of a drive current of a Z-pinch ICF (Inertial Confinement Fusion) is met.

A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.