79results about "Pulse generation by bulk negative resistance devices" patented technology

An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.

A bootstrap gate driver including a load indication unit, a bootstrap gate-drive unit and a drive-control unit is provided. The load indication unit is configured to generate a load indication signal in response to a state of a load. The bootstrap gate-drive unit is configured to drive a switch-transistor circuit in response to an inputted pulse-width-modulation (PWM) signal, wherein the switch-transistor circuit has a high-side driving path and a low-side driving path. The drive-control unit is coupled to the load indication unit and the bootstrap gate-drive unit, and configured to enable or disable the high-side driving path in response to the load indication signal. In the invention, the operation of the low-side driving path is not affected by enabling or disabling the high-side driving path.

The principal reason that commercially available 10 gigabits per second electrical interconnect has not previously been available is that such interconnect structures possess too high a level of parasitic inductance, capacitance, resistance and conductance. These result in signal degradation as a result of attenuation, harmonic distortion and dispersion and so sufficiently error-free transmission of data has been virtually impossible for high data rates such as those around 5 gigabits per second and above. By providing compensation mechanisms, signal integrity is improved thus enabling reliable data transmission at data rates of 5 gigabits per second, 10 gigabits per second and above. Non-linear transmission lines are used to form these compensation mechanisms. The non-linear transmission line may take the form of a distributed diode, for example, formed from a layer of N-doped silicon covered on its top surface by a layer of platinum and on its bottom surface by a layer of silicon dioxide. Advantageously, voltage biased sections of NLTL are used to perform compensation for different regions of a signal pulse according to the particular voltage biasing used. A plurality of such voltage biased sections of NLTL may be connected in series in order to obtain improved signal compensation.

A relaxation oscillator is provided. A first current source provides a first current. A second current source provides a second current. A resistive element is coupled between the first current source and a ground. A capacitive element is coupled between the second current source and the ground. A comparator has a non-inverting input terminal, an inverting input terminal and an output terminal for outputting a compare result. A clock generator provides a clock signal according to the compare result. A switching unit alternately couples the non-inverting input terminal and the inverting input terminal of the comparator to the resistive element and the capacitive element according to the clock signal.

A method of fabricating a N+/P+ zener diode where the reverse breakdown occurs in a controlled, and uniform manner leading to improved speed of operation and increase in current handling capability.

A comparator is provided. The comparator includes a voltage generator, a buffer unit and a threshold control loop. The voltage generator has an output terminal for providing a reference voltage according to a constant current. The buffer unit provides an output signal according to a first input signal and a bias signal. The threshold control loop provides the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal. The output signal represents a compare result of the first and second input signals. The buffer unit and the threshold control loop are powered by the reference voltage.

A method, circuit configuration and bridge circuit for charging a capacitance effective on the main current terminals of a semiconductor switch, in particular an intrinsic capacitance, in particular the drain-source capacitance of a MOSFET semiconductor switch or the collector-emitter capacitance of an IGBT semiconductor switch, the precharging, in particular the at least partial charging, of the effective capacitance being forcibly controlled via a charging current path.

A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.

A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through SubstrateVia insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A seconddie is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connectingdevice and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

A direct conversion RF transceiver (2) and ASIC having an on-chip voltage controlled oscillator operating frequency that is half of the transmitter (4) and/or receiver (6) operating frequency, the VCO (20) being comprised of a plurality of synchronized LC oscillators (92A-D) introducing precise phase shifts that eliminate frequency ambiguity. The transceiver incorporates several low power circuits, including on-chip a power converter switchably coupling a capacitor (42) to a power supply (45) and to an electrical load (40), multiple switchable low dropout regulators (60A, B) each coupled to alternate power supplies (62,64) and having electrical components (67A, B) for setting the bandwidth of the respective low dropout regulator. The transceiver also includes a FSK digital modulator utilizing a circuit-implemented polynomial piecewise approximation (71) of a raised cosine signal.

An oscillator outputs a sine wave with high purity capable of reducing phase noise. In a Colpitts oscillator circuit using a transistor as an amplifying part, a quartz-crystal resonator for waveform shaping is provided outside or inside an oscillation loop. A quartz-crystal resonator for oscillation and the quartz-crystal resonator for waveform shaping are formed, with an electrode pair and an electrode pair being provided on a common quartz-crystal piece. A separation distance between the electrode of the quartz-crystal resonator and the electrode of the quartz-crystal resonator is set large so that they are not elastically coupled, or even when they are elastically coupled, their coupling degree is weak, and an inductor causing parallel resonance with a parallel capacitance of the quartz-crystal resonator is provided.

A peak phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the pulse difference signal and provides a peak phase error value representing peak phase error between the clock signals. The delay and register logic may include a delay line with multiple delay cells and taps coupled in series in which each tap provides an output state of a delay cell. The register logic registers a state of each tap to provide delay bits in response to each trailing edge of the difference pulses. Each delay bit remains set until reset so that the longest pulse difference signal is registered to provide the peak phase error.

An oscillator comprising a compensation circuit, an oscillating module and a controller are disclosed. The compensation circuit comprises a charging circuit and a discharging circuit. The charging circuit comprises a first current source coupled between a voltage source and a second transistor, and the second transistor having a second first terminal coupled to a first current source, a second second terminal coupled to a first node, and a second gate for receiving a first switching signal. The discharging circuit comprises a third transistor having a third first terminal coupled to the first node and a third gate for receiving a second switching signal, and a second current source coupled between the third transistor and ground. The oscillating module couples between the compensation circuit and the controller and generates an output signal. The controller generates the first switching signal and the second switching signal according to the output signal.

A receiving circuit with a simple circuit structure for performing wireless communication utilizing electromagnetic induction is provided. An LSI chip and a storage medium where wireless communication utilizing electromagnetic induction is performed and the circuit scale and circuit size can be reduced are provided. The following receiving circuit may be used: a parallel circuit where two diode elements whose directions are opposite are connected in parallel is used, one end of the parallel circuit is connected to the other end of a coil whose one end is connected to a ground potential line, and a capacitor is connected in series with the other end of the parallel circuit. A transistor whose leakage current is markedly reduced may be used as a diode in the receiving circuit. Such a receiving circuit may be used in an LSI chip or a storage medium.

An oscillation circuit includes a condenser, a charging/discharging part configured to switch between charging and discharging of the condenser according to a control signal, a comparator configured to compare a voltage of the condenser with a reference voltage and output a comparison result signal, a flip-flop configured to be set or reset according to the comparison result signal, supply an output signal as the control signal to the charging/discharging part, and output the output signal as an oscillation signal, and a current control part configured to control an operating current of the comparator in correspondence with the voltage of the condenser.