5 results about "Micro array" patented technology

A device for examining samples is disclosed, comprising a microarray, an excitation light source, and an image sensor (10). The image sensor (10) has a plurality of SPAD arrays (11), a plurality of additional photodiodes (12), and computing electronics. The SPAD arrays (11) are configured to detect the decay behavior of fluorescence light emitted as a result of irradiation with excitation light (L) in a respective detection area of ​​the SPAD array (11). The additional photodiodes (12) are configured to measure the respective intensity of the excitation light (L) incident on each of them. The computing electronics are configured to determine a normalized decay behavior of fluorescence light for one or more of the SPAD arrays (11) from the detected decay behavior and at least one of the measured intensities of the excitation light (L).Furthermore, a method for examining a sample is disclosed.

This invention belongs to the field of optoelectronic technology, specifically relating to a method for fabricating a controllable crystallization micron-scale perovskite light-emitting device based on solution pretreatment. The method includes the following steps: Step 1: Obtaining a patterned microporous substrate; Step 2: Pre-wetting and seed layer construction; Step 3: Deposition of the main perovskite layer; Step 4: Slow-release controllable crystallization; The spin-coated wet film is placed in a vapor atmosphere of a good solvent for treatment, followed by thermal annealing to form a perovskite thin film within the patterned micropores; Step 5: Fabrication of a controllable crystallization micron-scale perovskite light-emitting device based on solution pretreatment. This invention, using pre-wetting, seed guidance, slow-release crystallization, and vapor annealing on a patterned microporous substrate, achieves precise control over the entire process of film nucleation and growth kinetics within the confined space of the micropores, thereby achieving high-quality, uniform fabrication of perovskite thin films within micron-scale micropores, and ultimately obtaining a high-performance, highly uniform microarray perovskite light-emitting device.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

The application relates to the technical field of electronic equipment, in particular to a shell, a display cover plate and electronic equipment, wherein the shell comprises a shell body, the shell body comprises a base and a microarray layer, the base has an inner surface and an outer surface, the microarray layer is arranged on the outer surface, the microarray layer comprises a plurality of spaced-apart bosses, the axial cross-sectional diameter of the boss is D, the height of the boss 121 is H, the distance between two adjacent bosses is L, 10 nm<=D<=1.8 mu m, H>=100 nm, 10 nm<=L<=1.8 mu m, and H / (L+D)>=1. In the application, a cavity is formed between the bosses, electromagnetic waves can resonate in the cavity, the emissivity is improved, and the heat dissipation efficiency of the electronic equipment is improved. According to the scheme, the emissivity of the shell in the 2.5 mu m-25 mu m wave band can be improved to >=88% without affecting the appearance of the shell surface, so that the shell can be applied to various application scenarios.

A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.