9results about How to "Does not affect operating efficiency" patented technology

The invention belongs to the technical field of integrated circuit manufacturing processes, and discloses a manufacturing method of a direct-current high-voltage bus filter, which comprises the following steps of: riveting a first group of embedded nuts on a connecting copper bar; acquiring a first image of the riveting connection copper bar, and judging whether the riveting connection copper bar is qualified or not; performing injection molding on the second group of embedded nuts and the qualified riveting connection copper bar to obtain a connection copper bar injection molding piece; collecting a second image of the connecting copper bar injection molding part, and judging whether the connecting copper bar injection molding part is qualified or not; the capacitor X and the capacitor X2 are installed in the installation grooves of the qualified connecting copper bar injection molding part; welding a Y capacitor and a Y2 capacitor with a grounding copper bar, and then loading the Y capacitor and the Y2 capacitor into a mounting groove of a connecting copper bar injection molding piece; mounting a magnetic ring in a magnetic ring fixing groove connected with the copper bar injection molding part; and welding each capacitor with the positive and negative copper bars to obtain the direct-current high-voltage bus filter. According to the invention, on-line quality inspection of the direct-current high-voltage bus filter can be realized, and the yield and the production efficiency are improved.

The invention provides a quantum computer benchmark test system, which is used for evaluating the performance of a quantum computer, and comprises a virtual quantum computer used for storing the information of a quantum computer to be tested; the test set generation module is used for constructing an initial test circuit set based on the to-be-tested quantum computer information stored by the virtual quantum computer; the test set preprocessing module is used for compiling circuits in the initial test circuit set to obtain a target test circuit set; the execution module is used for transmitting the target test circuit set to the quantum computer to be tested through a quantum computer interface arranged on the execution module so as to execute each circuit in the target test circuit set, and transmitting an execution result of each circuit to the evaluation module; and the evaluation module is used for evaluating the performance of the quantum computer to be tested.

The invention relates to a computing cluster. The computing cluster comprises a management platform, a Kubernetes cluster and a high-performance computing cluster, and the Kubernetes cluster comprises a master control Kubernetes node and a plurality of common Kubernetes nodes. Wherein the management platform is used for issuing an instruction of newly adding the high-performance computing node to the master control Kubernetes node under the condition of receiving a node newly adding request of the high-performance computing cluster. And the master control Kubernetes node is used for responding to the instruction of the newly added high-performance computing node and starting a target Kubernetes node, and the target Kubernetes node is an idle common Kubernetes node. And the target Kubernetes node is used for generating a high-performance computing node configuration file and requesting the high-performance computing cluster to be added to the high-performance computing cluster. According to the computing cluster provided by the invention, the high-performance computing cluster and the K8S cluster are fused as one computing cluster, and the operation efficiency of the high-performance computing cluster and the K8S cluster is improved.

The application provides a method, device, medium and program product for obtaining temporary file storage space, which is applied to the alignment packaging mode of APK of an Android system, and comprises the following steps for each aligned and packaged APK: a first local file header of a file is scanned to determine the size L of file data in the file; S12, the starting address Addr1 of the first local file header and the total length Lf of the first local file header are obtained; S13, the ending address Addr2 of the file data in the file is calculated, Addr2 = Addr1 + Lf + L; S14, the address range [Addr2 + 1, the ending address of the storage space corresponding to the file] is mapped to the tail of a predetermined temporary file storage area by using a memory mapping function of the Android system; and S15, the above steps S11 to S14 are performed for all M files contained in the APK. By mapping the unused storage space from the APK alignment file storage area to the temporary file storage area, the running efficiency of the system and the use efficiency of the storage space are improved.

The present application relates to the technical field of urban intelligent traffic control, and discloses a method for calculating the three-level utilization rate of reserved bus lanes and identifying space-time resources, aiming to solve the problems of rough resource quantification, fuzzy identification of residual space-time resources, and lack of theoretical basis for reservation of road rights. The steps of the present application are as follows: S1, based on the virtual occupation space of buses, discretize the bus lane into three levels of space, i.e. grid, road section and route, and construct a digital road network; S2, fuse bus GPS trajectory, signal timing and traffic flow data to analyze the space-time law of vehicle operation; S3, calculate the utilization rate of bus lanes step by step; S4, identify the residual space-time resources according to the utilization rate to provide support for dynamic allocation of reservation road rights. The present application realizes fine quantification and dynamic identification of lane resources, guarantees bus priority while improving lane utilization rate, provides data support for reservation of road rights, and is suitable for intelligent control and road right optimization of urban reserved bus priority lanes.

The invention relates to the technical field of elevators, and particularly discloses an elevator car door telescopic sill structure and an elevator, the elevator car door telescopic sill structure comprises a car bottom plate, two sliding door plates and a plurality of sill strips; a plurality of sliding rail assemblies are arranged at the bottom of the lift car bottom plate. Sliding push plates are arranged on the lower portions of the sides, away from each other, of the two sliding door plates correspondingly. The two sliding push plates are provided with guide inclined grooves correspondingly, and the number of the guide inclined grooves is consistent with that of the sill strips. A plurality of sliding rail assemblies are arranged on the two sliding door plates, a plurality of sill strips are arranged above the sliding rail assemblies in a sliding mode correspondingly, guide straight grooves are formed in the upper surfaces of the sill strips correspondingly, and rolling shafts correspondingly embedded into the guide inclined grooves are installed in the guide straight grooves correspondingly. The phenomena of shielding and people stumbling can be avoided, jolting and vibration caused by a gap of a hall car door sill when the AGV enters and exits from the car can be avoided, the operation efficiency of an elevator is not affected, and the space of the car is not occupied.

This invention discloses a control method for improving the transient stability of doubly-fed induction generator (DFIG) wind turbine systems connected to the grid, belonging to the fields of wind power grid connection technology and power system stability control technology. First, a reduced-order model of the system is established to accurately reflect the dynamic behavior during low-voltage ride-through. Based on this model, the attraction domain boundary and maximum power angle constraint are obtained, and then adaptive current reference control is proposed: the rotor d-axis current limit is calculated based on the maximum power angle constraint and the grid voltage, and compared with the original reference generated by maximum power point tracking. The smaller value is taken as the command to achieve adaptive limiting of the rotor current. Simultaneously, transient pitch collaborative control is proposed: the rotor speed is monitored in real time, and when the speed exceeds the safe upper limit, a transient load reduction power command is calculated and the pitch angle is rapidly increased to reduce mechanical torque. This invention can significantly enhance the fault ride-through capability and grid-connected operation reliability of DFIG wind turbines during transient processes such as voltage dips.

The invention provides a temperature control system and method for process liquid and semiconductor wet processing equipment. The temperature control system comprises a constant-temperature water unit, a first temperature control unit and a second temperature control unit, a flow path of the process liquid sequentially flows through the first temperature control unit and the second temperature control unit, and a water outlet of the constant-temperature water unit is connected with inlets of heat exchange channels of the two temperature control units in parallel so as to achieve two-stage temperature adjustment of the process liquid. According to the technical scheme, coarse adjustment and fine adjustment control over the temperature of the process liquid is achieved mainly through a two-stage temperature control framework with the process liquid connected in series and the constant-temperature water connected in parallel, and the accuracy and stability of the temperature of the process liquid in the wet process can be guaranteed. Moreover, the temperature control operation is continuously carried out, and generally, the temperature control operation does not occupy extra process takt time, so that the operation efficiency of wet processing is not influenced.

The invention belongs to the technical field of integrated circuit manufacturing processes, and discloses a manufacturing device of a direct-current high-voltage bus filter, which is characterized in that a pressing rivet module rivets and presses a first group of embedded nuts onto nut through holes of a connecting copper bar to form a riveted and pressed connecting copper bar; collecting a first image of the riveting connection copper bar; judging whether the riveting connection copper bar is qualified or not according to the first image; the injection molding module is used for carrying out injection molding on the second group of embedded nuts and the qualified riveting connection copper bar to obtain a connection copper bar injection molding part; collecting a second image of the connecting copper bar injection molding part; and judging whether the connecting copper bar injection molding part is qualified or not according to the second image. According to the invention, on-line quality inspection of the direct-current high-voltage bus filter can be realized, and the yield and the production efficiency are improved.