30results about How to "Improved Threshold Voltage Stability" patented technology

A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n⁺ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer.

The invention belongs to the semiconductor material and device field and discloses a GaN-based field effect transistor with a high quality MIS structure and a preparation method of the GaN-based field effect transistor, in particular, a GaN MISFET device gate dielectric layer and an improvement method of a dielectric layer and GaN interface. The device includes a substrate, an epitaxial layer grown on the substrate as well as a gate electrode, a source electrode, a drain electrode and an insulating layer; the epitaxial layer includes a stress buffer layer which is formed through primary epitaxial growth, a GaN epitaxial layer as well as a second epitaxial layer and a third epitaxial layer which are grown on selective regions on the GaN epitaxial layer; a GaN/AlGaN heterostructure is formed through secondary epitaxial growth, and groove channels are formed; an AlN thin layer is formed through third epitaxial growth; the AlN thin layer is partially oxidized so as to form an AlN/oxide dielectric layer stack structure; gate metal covers the groove channels; a source electrode region and a drain electrode region are formed at two ends; and the source electrode region and the drain electrode region are covered with metal, so that the source electrode and the drain electrode can be formed. The device and preparation process of the invention are simple and reliable. With the preparation method adopted, the high quality MIS structure can be formed, and the performance of the GaN MISFET device can be improved. The preparation method can play a key role in decreasing the electric leakage of the gate electrode, decreasing the resistance of the channels and stabilizing threshold voltage.

A switch device according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; and a switch layer provided between the first electrode and the second electrode, and the switch layer includes one or more kinds of chalcogen elements selected from tellurium (Te), selenium (Se), and sulfur (S) and one or more kinds of first elements selected from phosphorus (P) and arsenic (As), and further includes one or both of one or more kinds of second elements selected from boron (B) and carbon (C) and one or more kinds of third elements selected from aluminum (Al), gallium (Ga), and indium (In).

Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×10¹¹/cm⁻², and methods for forming such memory cells.

The invention relates to a readout circuit and a readout method for an electrically erasable read-only memory. The readout circuit comprises a comparator, a reference resistor, a sensing resistor, a reference unit and a storage unit, wherein the readout circuit is only configured with one reference unit, and the same reference unit is used in the process of reading operation; the threshold voltage of the reference unit is set into neutral threshold voltage; and the voltage on a reference unit control grid is set into a fixed value, so that the configuration time in the manufacturing process is obviously reduced, and the threshold added on a storage unit control grid is changed along with operating modes. Meanwhile, the voltage added on the storage unit control grid during the reading operation and programming verification operation is lower than that in the prior art, so that a stress effect of grid voltage is reduced, and the threshold voltage of the reference unit is set to a value approaching the neutral threshold voltage so as to be more stable.

The invention discloses a GaN E/D integrated device production method based on a two-step oxidation method. Based on the traditional depletion A1GaN(A1InN)/ A1N/GaN heterostructure, the barrier layer thickness can be controlled accurately by using the oxidation method, and the thickness of the barrier layer can be reduced to a half of the original thickness after the first oxidation process, and the high concentration electron gas can be maintained in the channel, and the medium generated by the oxidation can be used as the D-mode device gate dielectric. The medium of the E-mode device gate dielectric area can be removed, and the barrier layer can be consumed completely after the second oxidation process, and the two-dimensional electron gas can be consumed in the channel, and at the same time, the E-mode device gate dielectric can be generated. The same two-step oxidation technologies can be completed, the E-mode device technology and the D-mode device technology can be completely compatible, and the thicknesses of the gate dielectrics are the same, and therefore the device structures and the device performances can be cooperated with each other. The production of the E-mode device can be realized by using the oxidation method to reduce the thickness of the barrier layer, and the processing controllability is high; the E-mode technology and the D-mode technology can be completely compatible, and the thickness of the E-mode device gate dielectric and the thickness of the D-mode device gate dielectric are the same, the performances are cooperated with each other, and then the yield of the GaN E/D integrated circuit can be improved.

A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction of the microcrystalline silicon film (5) is above 80%. According to the invention, the transistor (1) includes a plasma treated interface (4) located between the insulator (3) and the microcrystalline silicon film (5) so that the transistor (1) has a linear mobility equal or superior to 1.5 cm2V−1s−1, shows threshold voltage stability and wherein the microcrystalline silicon film (5) includes grains (6) whose size ranges between 10 nm and 400 nm. The invention concerns as well a display unit having a line-column matrix of pixels that are actively addressed, each pixel comprising at least a transistor as described above.

Structures, devices and methods are provided for forming an interface protection layer (204) adjacent to a fully or partially recessed gate structure (202) of a group III nitride, a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) device or a metal-insulator-semiconductor field-effect transistor (MIS-FET) device, and forming a gate dielectric (114) disposed on the interface protection layer (204).

The present disclosure demonstrates that the introduction of electron deficient fullerene acceptors into thin films comprised of the high-mobility semiconducting polymers suppresses an undesirable “double-slope” in the current-voltage characteristics, improves operational stability, and changes ambipolar transport to unipolar transport. Examination of a variety of high μ polymers shows general applicability. The present disclosure also shows that instability is further reduced by tuning the relative electron affinity of the polymer and fullerene by creating blends containing different fullerene derivatives and semiconductor polymers. One can obtain hole μ values up to 5.6 cm² V⁻¹ s⁻¹ that are remarkably stable over multiple bias-sweeping cycles. The results provide a simple, solution-processable route to dictate transport properties and improve semiconductor performance in systems that display similar non-idealities.

The invention provides a light sensation detection device and a display terminal which are applied to the technical field of display. In the light sensation detection device, a power supply module comprises a control unit and a processing unit which are connected with each other to output a first voltage, a second voltage and a third voltage; a detection module is connected with the power supply module, and comprises a first bridge arm and a second bridge arm which are connected in parallel to receive a first voltage, a second voltage and a third voltage, an upper switching tube of the first bridge arm and a lower switching tube of the second bridge arm are photoinduction switching tubes, the midpoint of the first bridge arm outputs a first detection signal, and the midpoint of the secondbridge arm outputs a second detection signal; and the work period of the light sensation detection device comprises a first time period and a second time period, and the first voltage is higher than the second voltage in the first time period and lower than the second voltage in the second time period. According to the light sensation detection device and the display terminal, light sensation errors can be reduced, the device stability is enhanced, and the sensitivity of an automatic backlight system of the display terminal is improved.