53results about How to "Occurrence is very low" patented technology

A hydrogel polymer obtained by polymerizing a monomer component including acrylic acid (salt) is post-neutralized so that each of polymer particles derived from a polymer produced by neutralizing the hydrogel polymer has an allowable neutralization ratio. The polymer as obtained by neutralizing the hydrogel polymer is reacted with a crosslinking agent reactive to a functional group of the polymer. The allowable neutralization ratio, for example, is a neutralization ratio which is not lower, by not less than 20 mole percent, or more than, at least 55 mole percent, than an average neutralization ratio of a mass of the polymer particles, and the post-neutralization is carried out so that a number of polymer particles having a non-allowable neutralization ratio outside the allowable neutralization range is not more than 10 in 200 polymer particles, thus obtaining a water-absorbent agent having high absorbency under no applied pressure and high pressure wherein the amount of water soluble component is lower compared with the conventional water-absorbent agent and a change in pH of a swollen gel is small.

The present invention's manufacturing method for a sealed battery includes: a process whereby a sealed battery application electrode assembly 11 is formed that has multiple positive electrode substrate exposed portions 14 at one end and multiple negative electrode substrate exposed portions 15 at the other end; a process whereby the negative electrode collector 181 and negative electrode collector receiving part 183 are brought against both surfaces of the part to be welded on at least the negative electrode substrate exposed portions 15, with tape 23a constituted of thermodeposited resin and having an opening 231 in the center being interposed; and a process whereby resistance welding is effected by passing current between the negative electrode collector 181 and negative electrode collector receiving part 183 positioned at the two sides.

A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.

A solder paste comprising a solder alloy powder and a flux. The volumetric expansion at the time of melting of the solder alloy is at most 0.5%. The flux contains a bisphenol A epoxy resin and a curing agent selected from a carboxylic anhydride and a dicarboxylic acid. The solder paste can be used in applications suitable for high-temperature solders. The solder alloy has an alloy composition comprising, in mass percent, 70-98% of Bi, a total of 0-0.5% of at least one substance selected from Ag, Cu, Sb, In, Zn, Ni, Cr, Fe, Mo, P, Ge, and Ga, and a remainder of Sn.

A control method and architecture for controlling transmission of streaming audio / video data are disclosed. The method uses a report transmission rate on a transmitter to reduce the playback latency on a receiver. The report transmission rate is determined according to an actual transmission rate and the residual data amount of the previous period of a transmitter buffer. The actual transmission rate is the minimum of an available transmission rate and a required transmission rate, which depends on the residual data amount and the report transmission rate. Therefore, the report transmission rate is adjusted according to the accumulation of residual data of transmitter buffer, which improves the playback latency.

A transmission synchromesh is provided that includes a pressure element coupled to a synchronizing ring, and one shift sleeve, wherein the pressure element for detent permits an axial position displacement of the shift sleeve relative therewith. A pressure element and a transmission synchromesh method for improved synchronization are also provided.

A method of forming surface irregularities comprises preparing a GaN substrate; forming a mask on a surface of the GaN substrate, the mask defining a surface-irregularity formation region; and wet-etching portions of the surface of the GaN substrate by using the mask as an etching mask. The wet-etching of the GaN substrate is performed until the end of one surface of the GaN substrate to be formed by the wet-etching using the mask meets the end of another surface of the GaN substrate to be formed by the wet-etching using the mask, the another surface being adjacent to the one surface.

A gas generator for health is provided. The gas generator for health includes an electrolysis device, a gas mixing chamber and a gas output device. The electrolysis device is for electrolyzing water to produce a combination gas including hydrogen and oxygen. The gas mixing chamber includes a shell and a cover. The shell has an anti-explosion hole. The cover is separatably disposed on the anti-explosion hole, and the diameter of the anti-explosion hole is larger than 0.5 cm. The gas mixing chamber is connected to the electrolysis device for receiving the combination gas. A vaporized gas is generated by the gas mixing chamber and mixed with the combination gas to produce a healthy gas. The gas output device is connected to the gas mixing chamber for outputting the healthy gas to a user to breath.

An object of the present invention is to provide an efficient method for manufacturing a p-type group III nitride semiconductor that has adequate carrier concentration and a surface with a low occurrence of crystal damage. The inventive method for manufacturing a p-type group III nitride semiconductor comprises: (a) growing a group III nitride semiconductor containing a p-type dopant at 1000° C. or higher in an atmosphere containing H2 gas and / or NH3 gas; and (b) after the growth of the group III nitride semiconductor, substituting the H2 gas and NH3 gas with an inert gas at a temperature higher than 800° C. while reducing the temperature.

A sealed battery including: an electrode assembly 11 having multiple positive electrode substrates exposed at one end and negative electrode substrates exposed at the other end; and collectors 181 and collector receiving parts 183 that are resistance-welded on both sides of the multiple positive or the multiple negative electrode substrates or both, grooves 23 being formed around the resistance-welded portion of at least one of the collector 181 and the collector receiving part 183. Due to the spattered particles 26 generated during the resistance-welding being captured within the grooves 23, few particles burst into the inside of the electrode assembly 11 or into the outside.

An epitaxial wafer is produced by a method comprising steps of growing a silicon single crystal ingot having a given oxygen concentration through Czochralski method, cutting out a wafer from the silicon single crystal ingot, subjecting the wafer to a heat treatment at a given temperature for a given time, and epitaxially growing the wafer.

The present invention discloses a compound semiconductor epitaxial wafer and its fabrication method. The method comprises the steps of the followings: depositing a first buffer layer of silicon on a silicon substrate; depositing a compound semiconductor second buffer layer on the first buffer layer; growing a compound semiconductor first epitaxy layer on the second buffer layer; reducing the threading dislocation density by a thermal treatment, which is caused by the discrepancy in the lattice constants or in the thermal expansion coefficients of the silicon substrate and the compound semiconductor epitaxy layers; growing a compound semiconductor second epitaxy layer on the first epitaxy layer; and, applying a thermal treatment again. Accordingly, a compound semiconductor epitaxy layer with excellent crystal quality is obtained.

A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.

A fluororesin composition comprising a mixture of a fluororesin and carbon nanotubes whose surfaces have been treated with a fluorine-based surfactant is described. The fluororesin composition of the present invention has enhanced conductivity, electrostatic charge properties, and other electrical properties.

Disclosed are an actinic ray-sensitive or radiation-sensitive resin composition including (A) a compound capable of generating an acid by irradiation of actinic rays or radiation, and (B) a resin of which solubility in an alkali developer increases by being decomposed by the action of an acid, and, a resist film, a pattern forming method, an electronic device manufacturing method, and an electronic device, each using the composition, wherein the actinic ray-sensitive or radiation-sensitive resin composition contains at least one type of a specific compound represented by General Formula (A-I) and at least one type of a specific compound represented by General Formula (A-II) as the compound (A).

Disclosed are a polishing pad used in a CMP process of a planar material such as a silicon wafer, plate glass for a display, etc. and a method for manufacturing the same. The polishing pad comprises a non-woven fabric consisting of ultrafine fibers and elastomeric polymer impregnated into the fabric, on which the ultrafine fibers are raised and arranged to simultaneously satisfy the following conditions (I) to (III) such that the ultrafine fibers are oriented in a longitudinal direction to a central axis:The polishing pad of the present invention includes ultrafine fibers, which are arranged at a relatively wide orientation angle and have pores formed therebetween without requiring alternative processes for forming the pores, thus, exhibits excellent polishing performance and low occurrence of scratches during a polishing process.

The present invention relates to a method for using Prowashonupana barley to produce a food product comprised primarily of the Prowashonupana barley. The resultant food product is desired because, when consumed, it does not contribute to significantly elevated glycemic indices in a host, as indicated by the rapidly available glucose (RAG) assay.

A 3-dimensional flash memory device and methods of fabricating and driving the same are provided. The device includes: a channel layer extending over a substrate in a first direction perpendicular to a surface of the substrate; an information storing layer extending along a sidewall of the channel layer in the first direction; control gates each surrounding, the channel layer, with the information storing layer between the channel layer and the control gates; an insulating layer being between the control gates in the first direction and separating the control gates from each other; a fixed charge region disposed at an interface of the insulating layer and the information storing layer or in a portion of the information storing layer between the control gates in the first direction; and a doped region induced by the fixed charge region and disposed at a surface of the channel layer facing the fixed charge region.

Provided are: a polyethylene laminate that exhibits excellent flexibility, barrier properties, and cleanliness (a low occurrence of fine particles), that does not deform even after sterilization treatment at 121° C., and that maintains high transparency; and a medical container using same. The medical container is configured by layering: an outer layer and an inner layer that comprise from 20 to 80 wt % of a high-density polyethylene (A) having specific properties, from 0 to 50 wt % of a linear low-density polyethylene (B1), and from 5 to 40 wt % of an ethylene-based polymer (C); and an intermediate layer that comprises from 10 to 40 wt % of the high-density polyethylene (A) and from 60 to 90 wt % of the linear low-density polyethylene (B1).

The present invention is to provide a fastener for an ornament having a pin which is excellent in workability on assembly and manufacture and improved in yield ratio, and the fastener of the present invention is characterized that the pin of the ornament is clamped in the fastener and retained between the respective spherical surfaces of a plurality of small balls, wherein a column portion inside a housing is provided with an outer column portion of a cylindrical body which is formed integrally with a pin retaining portion in a direction at which the pin retaining portion is pulled backward and internally has a through hole in the same direction as a direction at which the pin is inserted and an inner column portion of a cylindrical body which is inserted and fixed to the through hole inside the outer column portion, formed integrally with the control lever in a direction at which the control lever is urged and also has a through hole acting as a passage for introducing the pin inserted through the pin passing hole.

A mask-integrated surface protective tape for production of semiconductor chips, with the production containing steps (a) to (d), which tape comprises a base film and a mask material layer provided thereon, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is from 20.0 mN / m to 48.0 mN / m, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range from 0.05 μm to 2.0 μm when measured in conformity to JIS B0601,(a) a specific laminating step;(b) a specific peeling step;(c) a specific plasma-dicing step; and(d) a specific ashing step.

In order to improve an intermediate plate for the sealing of mutually opposed sealing faces of housing parts of a control unit for fluid-operated consuming devices, comprising two seal surface regions of at least one seal layer which face toward the respective sealing faces and are placeable sealingly thereon, so that a lasting and reliable sealing between the seal surface regions and the sealing faces is ensured, it is proposed that at least one of the seal surface regions is formed by an exposed metal coating which is capable of sliding relative to the sealing faces, for direct contact with the sealing faces.