81 results about "Characterization test" patented technology

Test pads, methods, and systems for measuring properties of a wafer are provided. One test pad formed on a wafer includes a test structure configured such that one or more electrical properties of the test structure can be measured. The test pad also includes a conductive layer formed between the test structure and the wafer. The conductive layer prevents structures located under the test structure between the conductive layer and the wafer from affecting the one or more electrical properties of the test structure during measurement. One method for assessing plasma damage of a wafer includes measuring one or more electrical properties of a test structure formed on the wafer and determining an index characterizing the plasma damage of the test structure using the one or more electrical properties.

A laser system using ultrashort laser pulses is provided. In another aspect of the present invention, the system includes a laser, pulse shaper and detection device. A further aspect of the present invention employs a femtosecond laser and a spectrometer. Still another aspect of the present invention uses a laser beam pulse, a pulse shaper and a SHG crystal. In yet another aspect of the present invention, a multiphoton intrapulse interference phase scan system and method characterize the spectral phase of femtosecond laser pulses. Fiber optic communication systems, photodynamic therapy and pulse characterization tests use the laser system with additional aspects of the present invention.

A laser system using ultrashort laser pulses is provided. In another aspect of the present invention, the system includes a laser, pulse shaper and detection device. A further aspect of the present invention employs a femtosecond laser and a spectrometer. Still another aspect of the present invention uses a laser beam pulse, a pulse shaper and a SHG crystal. In yet another aspect of the present invention, a multiphoton intrapulse interference phase scan system and method characterize the spectral phase of femtosecond laser pulses. Fiber optic communication systems, photodynamic therapy and pulse characterization tests use the laser system with additional aspects of the present invention.

A patch or set of patches may be deployed, often to a subset of potentially vulnerable systems, to address a particular vulnerability while providing a facility to monitor and, in some cases, characterize post-patch exploit attempts. Often, such a patch will check for an exploit signature and, if an exploit attempt is detected or suspected, take an appropriate action. For example, the patch may include code to log indicative data or trigger such logging. In some exploitations, the patch may generate or contribute to a warning or advisory regarding an additional target (or targets) of the exploit and, if appropriate, initiate a patch or protective measure for the additional target(s). In some exploitations, the patch may simulate responses or behaviors suggestive (to an attacker) of unpatched code. In some exploitations, the patch may direct an exploit attempt to a service (or simulated service) hosted or executing in an isolated protection domain.

The present invention pertains to semiconductor memory devices, and particularly to a system and method for adaptively setting the operating voltages for SRAM for both Vtrip and SNM to reduce power while maintaining functionality and performance, based on modeling and characterizing a test structure. One embodiment comprises an SRAM array, a test structure that characterizes one or more parameters that are predictive of the SRAM functionality and outputs data of the parameters, a test controller that reads the parameters and identifies an operating voltage that satisfies predetermined yield criteria, and a voltage controller to set an operating voltage for the SRAM array based on the identified operating voltage. One method sets an operating voltage for an SRAM by reading test structure data of the parameters, analyzing the data to identify an operating voltage that satisfies predetermined yield criteria, and setting the operating voltage for the SRAM based on the identified operating voltage.

The present invention provides a flexible on-chip testing circuit and methodology for measuring I / O characterization of multiple I / O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise / fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.

Apparatus and methods are provided for analyzing surface characteristics of a test object using broadband scanning interferometry. Test objects amenable to these apparatus and methods include but are not limited to semiconductor wafers, semiconductor devices, metallic surfaces, and the like. An interferometry system is used to obtain an interferometry signal and related to data embodied in the signal representative of the test object surface. This signal and / or data is used to construct an n-dimensional function that includes an independent frequency variable and an independent time variable, and / or an n-dimensional function that includes an independent scale variable and an independent time variable, and / or a multi-domain function. These functions are compared with various models to obtain a best match that is then used to characterize the test object surface.

A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.