9 results about "Mosfet circuits" patented technology

This application provides a master-slave switching circuit based on USB 2.0 communication, including a communication circuit module and a charging circuit module. The charging circuit module includes a rectifier and filter circuit, a reverse connection protection circuit, a DC-DC circuit, and a Block MOSFET circuit connected in sequence. Power is supplied through a power connector to the rectifier and filter circuit, and then output to the HUB IC by the Block MOSFET circuit. The communication circuit module includes a Type-C interface and a Type-A interface, both integrated into a single communication signal transmitted to the vehicle's infotainment system via the HUB IC. Furthermore, a switching detection circuit and an output VBUS level control circuit are connected between the HUB IC and the vehicle's infotainment system for power management of the master-slave switching circuit. Through precise level detection and control, this application enables intelligent power switching, ensuring safe communication between the vehicle's infotainment system and external devices, enhancing device protection, and improving the user experience. This circuit design not only optimizes power management but also provides higher reliability and security for the vehicle's infotainment system.

The invention belongs to the MOSFET (metal-oxide-semiconductor field effect transistor) driving control technology, particularly relates to a solid-state power controller driving circuit based on a reference source circuit and a control method, and can be applied to the field of power distribution system power control. The solid state power controller driving circuit comprises a main control processor circuit, a reference source circuit, a follower circuit, an MOSFET driving circuit, an MOSFET circuit and an MOSFET parameter acquisition circuit, an output end main control I / O of the main control processor circuit is connected with an input end of the MOSFET driving circuit, and an input end MOSFET state acquisition I / O of the main control processor circuit is connected with an output end of the MOSFET parameter acquisition circuit; the output end of the reference source circuit is connected with the input end of the follower circuit; the output end of the follower circuit is respectively connected with the ground of the MOSFET driving circuit and the input end of the MOSFET parameter acquisition circuit; the input end of the MOSFET parameter acquisition circuit is connected with the output end of the MOSFET circuit; and the output end of the MOSFET driving circuit is connected with the input end of the MOSFET circuit.

A cascade MosFet circuit design for variable gear switching using pulse width modulation (PWM) between electronic gears to achieve a smooth transition is disclosed. In an embodiment, in the system, there can be three separate stages of two or more switches from very low amperage to hundreds of amps that can be automatically selected within a chosen stage. The automatic switching can be programmed to be power (e.g., current) sensitive or can be both power and electronic gear sensitive as to cascade into the right MosFet combination for different gear settings and still select greater values for varying power levels. Such a smooth transition can allow the generator or motor using such cascade MosFet circuit design to operate more efficiently and / or more quietly.

The application relates to a super-junction MOSFET device drift region parabolic variable resistance model and a modeling method, which comprises the following steps: constructing a super-junction MOSFET circuit model, wherein the model is composed of a MOSFET, a drift region parabolic variable resistance, a body diode and a first resistance I and a first resistance II; resistance modeling is carried out on the drift region of the super-junction MOSFET device according to the physical structure parameters of the super-junction MOSFET, and a parabolic variable resistance model of the drift region is obtained by adopting a parabolic approximation; a Taylor polynomial is introduced to describe a self-heating first resistance model. The parameters of the drift region parabolic variable resistance model are obtained through the physical structure parameters of the super-junction MOSFET device, the parameters of a conventional MOSFET model, the parameters of a body diode model and the parameters of a self-heating first resistance model are obtained through actual measurement data of the device. The application can well simulate the characteristics of the super-junction MOSFET device in various working regions, and the simulation accuracy is high.

Circuits and methods for high-quality amplifiers (e.g., low-noise amplifiers and power amplifiers) that are sensitive, provide good amplification, are physically compact, and can withstand relatively high drain-to-source voltages. Some embodiments include a thin gate oxide N-type MOSFET device or N-type Extended Drain MOSFET (NEDMOS) device co-fabricated with one or more serially-coupled thick gate oxide P-type Extended Drain MOSFET (PEDMOS) devices of several types. Some embodiments include one or more multi-gate NEDMOS devices. Embodiments includes PEDMOS devices having at least source and drain regions that include germanium (e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si and graded Ge and Si mixtures), particularly PEDMOS devices having a strained channel region. A significant benefit of the inventive IC structures and variants is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain / source regions.

A system and method for autonomous machine identity succession utilize a hardware-rooted semantic sentinel and an analog neuromorphic audit engine to ensure state integrity. The system detects micro-architectural threat signatures through continuous asynchronous voltage monitoring and gates cryptographic signatures via a low-impedance analog interlock circuit physically interposed on a processor signature-enable line. Behavioral integrity is verified through an adversarial “Proof of Logical Alignment” handshake, where proposed action vectors are audited via an analog memristor crossbar array utilizing physical current summation replicated through a high-impedance Wilson Current Mirror isolation barrier. The invention ensures the atomic migration of identities across heterogeneous hardware architectures through a “Handshake-and-Zeroize” protocol, utilizing a series-pass isolation switch and crowbar MOSFET circuit to provide irreversible thermodynamic destruction of the source state.

A current sensing circuit includes an output driving transistor with an output node that provides an output voltage; a diode-connected first transistor connected between the output node and a current circuit; a second transistor and a third transistor connected in series, the second transistor having a gate connected to a gate of the output driving transistor, and the third transistor having a gate connected to a gate of the first transistor; and a current measuring circuit connected in series with the second transistor and the third transistor to measure a current flowing through the second transistor and the third transistor.

Circuits and devices for a motor driver are described. A hybrid integrated circuit (IC) can include a driver IC, a first IC, and a plurality of second ICs. The first IC can include a plurality of high-side metal-oxide-semiconductor field-effect transistors (MOSFETs). The first IC can further include a common drain terminal connected to drains of the plurality of high-side MOSFETs. Each one of the plurality of second ICs can include a respective low-side MOSFET. The hybrid IC can further include a first set of bonding wires connecting the driver IC to the first IC. The hybrid IC can further include a second set of bonding wires connecting the driver IC to the plurality of second ICs. The hybrid IC can further include a third set of bonding wires connecting the first IC to the plurality of second ICs.

A vehicle fuel pump power management circuit that replaces traditional relay and fuse-based power routing with a MOSFET-based circuit controlled by the Automatic Shutdown Relay (ASD) and Engine Control Unit (ECU). The MOSFET circuit allows direct current flow from the vehicle's power supply to the fuel pump, enhancing reliability by reducing mechanical failures associated with conventional relays. A multi-layered PCB design minimizes electromagnetic interference, enhances heat dissipation, and prevents component overheating, while isolating circuits for optimized performance. The ECU provides real-time adjustments based on sensor feedback, ensuring efficient fuel injection timing.