This invention discloses a manufacturing method for improving the yield of
CMOS image sensors, comprising: S1, providing a
wafer including a substrate and a gate layer formed on the substrate, the gate layer having a plurality of spaced isolation trenches, and depositing a
silicon nitride barrier layer on the surface of the isolation trenches and on the gate layer; S2, depositing a first interlayer
dielectric layer, measuring and recording the thickness of the first interlayer
dielectric layer; S3, depositing a second interlayer
dielectric layer, measuring and recording the
total thickness of the first and second interlayer dielectric
layers, and calculating the thickness of the second interlayer
dielectric layer; S4, performing surface planarization, measuring and recording the
total thickness, and obtaining the
polishing thickness; S5, calculating the current thickness ratio of the second to the first interlayer
dielectric layer and outputting it to a
photolithography process module, and searching for the associated
etching deviation in a
database; S6, adjusting the critical dimensions of the
photolithography process according to the
etching deviation. This method facilitates data interaction between three processes, which helps to improve product yield and increase
mass production efficiency.