2results about How to "Reduce overall layout space" patented technology

This utility model provides a dust removal device, relating to the field of dust removal technology. The utility model includes a housing, a suction mechanism, and a filtration mechanism disposed within the housing. The suction mechanism includes a suction pipe and a suction pipe connected to the housing. A fan is mounted on the suction pipe, and the suction pipe draws in dust-laden gas. The filtration mechanism includes a bottom plate and a partition plate disposed within the housing. The suction pipe communicates with the upper space of the partition plate, and the suction pipe communicates with the lower space of the partition plate. The bottom plate is located below the air outlet end of the suction pipe. A filter channel is provided at the bottom of the partition plate, and a toothed plate is movably connected to the side wall of the filter channel. The housing above the bottom plate is filled with water at a level not higher than the bottom of the filter channel. This utility model removes dust and moisture from gas without the need for a large-scale dust removal system, using external air circulation.

A pixel circuit includes a first transistor, a scan line, a data line, a selection unit, a storage capacitor, and a pixel electrode. The first transistor includes a gate, a source, and a drain. The scan line is electrically connected to the gate of the first transistor. The data line is electrically connected to the source of the first transistor. The selection unit is electrically connected to the drain of the first transistor. A first terminal of the storage capacitor is electrically connected to the drain of the first transistor and an input node of the selection unit. The pixel electrode is electrically connected to an output node of the selection unit, and the selection unit provides a driving voltage to the pixel electrode. By setting the selection unit between the pixel electrode and the storage capacitor, the dielectric layer included in the selection unit increases the insulation capability, avoids the storage capacitor from being affected by the leakage current between the front panel stack and the pixel electrode and the leakage current between the pixel electrodes through the front panel stack material, and can preferably maintain the capacitance value of the storage capacitor. The capacitance value of the storage capacitor can be designed to be a smaller value, and the speed of data writing to the storage capacitor is improved. In this way, the element width of the first transistor can be reduced, and the load and layout space of the scan line and the data line can be reduced.