20 results about "Fermi level pinning" patented technology

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

The present invention provides a general salt-assisted chemical vapor deposition (SA-CVD) synthetic method for the high-yield preparation of 1D hexagonal-phase MxV6S8(M=K, Rb, Cs) and KxV6SySe8-y nanowires. The resulting nanowires exhibit typical metallic properties, which can be used as a good van der Waals contact for achieving high-performance fermi level pinning free transistors. The present synthesis method allows a more systematic investigation of the intrinsic properties of hexagonal-phase V6S8 structures.

The invention provides a preparation method of a Schottky contact for radiation detection based on a cadmium telluride single crystal, and solves the problems of Fermi level pinning and uncontrollable interface morphology of the cadmium telluride Schottky contact prepared by the existing method. The Schottky contact is successfully prepared by adopting a transfer method, the metal electrode and the substrate are separated by utilizing polydimethylsiloxane and a tungsten steel gold-plated probe through a mechanical stripping method, then the metal electrode is directly lapped on the clean cadmium telluride surface, and the adhesion between the polydimethylsilane and the metal electrode is reduced through heating, so that the Schottky contact is prepared. Finally, separation of the polydimethylsilane and the metal electrode and preparation of the cadmium telluride surface metal electrode are achieved.

The application discloses an Au-WS2-Au van der Waals Schottky junction type photoelectric sensing unit, preparation and application, and belongs to the technical field of semiconductor devices. The sensing unit is composed of a substrate, a two-dimensional material layer transferred by a dry method and an Au electrode, the two-dimensional material is preferably WS2, the Au electrode forms a van der Waals contact with the two-dimensional material and constitutes a Schottky junction; the structure can effectively inhibit Fermi level pinning effect, realize dynamic modulation of a Schottky barrier, and produce characteristic reverse-bipolar light response and stable spectral modulation varying with wavelength under the regulation of a gate; the occupied area is only about 73 mu m 2 , and the sensing unit can accurately reconstruct monochromatic and broadband spectra in the 380-680 nm visible light band, with an average reconstruction accuracy of 0.746 nm and a spectral resolution better than 10 nm. The sensing unit can be applied to a miniature computing spectrometer, effectively solves the technical defects of complex preparation and difficult regulation of existing devices, and meets the requirements of miniaturization and integration detection.

Contacts for solar cells and other optoelectronic devices are provided. Embodiments described herein take advantage of the surface Fermi level pinning effect to build an electrical field inside of a semiconductor to extract or inject carriers for solar cells, photodetectors, and light-emitting device applications. For example, n-type or p-type two-dimensional (2D) materials can be used in contact with an n-type semiconductor to form a “p-region” so that a p-n junction, or an i-n or n-n+ junction can be constructed. Similarly, n-type or p-type 2D materials can be used in contact with a p-type semiconductor to form an “n-region” so that an n-p junction, or an i-p or p-p+ junction can be constructed. These structures can provide sufficiently high electrical field inside the semiconductor to extract photogenerated carriers in solar cells and photodetectors or inject minority carriers for light-emitting devices.

The invention belongs to the technical field of ultra-wide bandgap semiconductors, and particularly relates to a power diode device and a preparation method thereof, MXene is adopted as a Schottky anode material, and the series resistance is remarkably reduced by using the ultrahigh conductivity of the MXene, so that the performance of the device in high-frequency and large-current application is improved. Meanwhile, by regulating and controlling the surface terminal and the element composition of the MXene, the flexible adjustment of the work function can be realized, so that the electron affinity of the MXene can be well matched with that of beta-Ga2O3, a higher Schottky barrier and an excellent rectification characteristic can be further obtained, and the reverse leakage current can be inhibited. In addition, as a two-dimensional material, MXene can form a uniform and flat Van der Waals contact interface, so that the damage of a high-energy process is avoided, the surface integrity of beta-Ga2O3 is maintained, the interface state and Fermi level pinning effect are effectively relieved, the barrier height better conforms to the theoretical design, and the Schottky diode with the performance closer to the ideal state can be realized.

This invention provides a room-temperature ultrasensitive hydrogen sensor based on a two-dimensional semiconductor Schottky junction, belonging to the field of semiconductor hydrogen sensor technology. By constructing a two-dimensional semiconductor Schottky junction with weak Fermi level pinning, the invention utilizes the specific reaction between palladium and hydrogen to reduce the work function, thereby causing a change in the Schottky barrier and current, achieving highly sensitive and specific detection of low-concentration hydrogen. The invention includes micro / nano electrodes fabricated by photolithography and two-dimensional semiconductor materials. The two-dimensional semiconductor and the palladium electrode form a weakly Fermi-level pinned Schottky junction through van der Waals contacts. This invention utilizes the specific reaction between palladium and hydrogen to reduce the work function of palladium, thereby causing a change in the potential barrier and a large current change in the weakly Fermi-level pinned two-dimensional semiconductor Schottky junction, achieving highly sensitive and specific detection of low-concentration hydrogen at room temperature.

The invention discloses a thin film transistor device based on a sandwich structure active layer and a preparation method thereof, relates to the technical field of electronic devices, and solves the problem of low device carrier concentration caused by scattering of moving electrons in the thin film transistor active layer. The thin film transistor comprises a substrate, a grid electrode, a grid insulating layer, a sandwich structure active layer, a source electrode and a drain electrode from bottom to top. Wherein the sandwich structure active layer sequentially comprises a wide-band-gap metal oxide semiconductor, a narrow-band-gap metal oxide semiconductor and a wide-band-gap metal oxide semiconductor from bottom to top. The sandwich-structured active layer has an energy band gap, so that a Fermi level pinning effect is caused, a structure similar to a two-dimensional electron gas is formed, electrons can be effectively limited to move near an interface of the active layer, scattering is reduced, the mobility and the electrical property of a thin film transistor device are enhanced, and the thin film transistor device is suitable for the OLED display technology and the OLED display technology. Wide application prospects are realized.

The present invention provides a general salt-assisted chemical vapor deposition (SA-CVD) synthetic method for the high-yield preparation of 1D hexagonal-phase MxV6S8(M=K, Rb, Cs) and KxV6SySe8-y nanowires. The resulting nanowires exhibit typical metallic properties, which can be used as a good van der Waals contact for achieving high-performance fermi level pinning free transistors. The present synthesis method allows a more systematic investigation of the intrinsic properties of hexagonal-phase V6S8 structures.

The invention provides a semiconductor device and a preparation method thereof, and an electronic product. The semiconductor device comprises a two-dimensional material layer; the tunneling layer is arranged on one side of the two-dimensional material layer along the thickness direction; the electrode structure is arranged on the side, away from the two-dimensional material layer, of the tunneling layer, the electrode structure comprises a first electrode and a second electrode which are arranged in a spaced mode in the first direction, and the first direction is parallel to the plane where the two-dimensional material layer is located; wherein the tunneling layer is made of gallium oxide. According to the semiconductor device provided by the invention, the gallium oxide insulating material is adopted between the electrode structure and the two-dimensional material layer to serve as the material of the tunneling layer, so that the contact quality between the two-dimensional material layer and the electrode structure can be optimized, the contact resistance and the Schottky barrier are reduced by using the quantum tunneling effect, the device performance is optimized, and the reliability of the device is improved. A good packaging effect can be achieved for the two-dimensional material layer, and the Fermi level pinning phenomenon and erosion of environmental pollutants such as water and oxygen can be effectively resisted.

The application discloses a kind of HfAlO x / graphene / HfAlO x Heterojunction phase modulator, preparation method and phase modulation method, the HfAlO x / graphene / HfAlO x Heterojunction, using HfAlO x As dielectric material, form good heterojunction structure with graphene.HfAlO x With high dielectric constant and good stability, can effectively regulate the electrical properties of graphene, while avoiding the Fermi level pinning effect when graphene is in direct contact with metal, improve the efficiency and flexibility of phase modulation.The whole structure length is only 800nm, much smaller than the free space wavelength of mid-infrared waveband, subwavelength operation is realized.This small size structure is conducive to the high integration and miniaturization of device, can be applied to high-density optical integrated chip, micro optical sensor and other fields, help to improve the integration and portability of system.

The embodiment of the invention provides a transistor based on a two-dimensional material, which comprises a substrate, a first MoTe2 layer, a source electrode metal layer, a drain electrode metal layer, a second MoTe2 layer and a grid electrode layer, and is characterized in that the first MoTe2 layer, the source electrode metal layer and the drain electrode metal layer are sequentially arranged above the substrate; the first MoTe2 layer is in n-type contact with the source electrode metal layer and the drain electrode metal layer through the Fermi level pinning effect, the second MoTe2 layer and the grid electrode layer are sequentially arranged above the first MoTe2 layer, and the second MoTe2 layer is in p-type contact with the source electrode metal layer and the drain electrode metal layer. According to the transistor provided by the embodiment of the invention, the transistor can be dynamically programmed into a p-type transistor or an n-type transistor by applying an external selection voltage, and the transistor has the advantage of being independent of doping based on regulation and control on a metal-semiconductor contact potential barrier, so that the technical complexity is reduced. The embodiment of the invention also provides a preparation method of the transistor based on the two-dimensional material.

The application relates to the field of semiconductor technology, in particular to a low-leakage-current GaN Schottky diode optimization method and system, which comprises the following steps: step one, substrate interface purification treatment: in-situ cleaning is performed on the surface of a gallium nitride substrate after epitaxial growth, surface-attached impurities and a surface natural oxide layer are removed, an atomic-level flatness contact interface is formed, and hybrid interference caused by surface defects is reduced. The application effectively alleviates the interface hybridization effect of direct contact between metal and gallium nitride through the interface decoupling effect of two-dimensional van der Waals materials, weakens the Fermi level pinning effect, and expands the regulation range of the Schottky barrier height; the substrate interface purification and crystal orientation calibration process reduces the interface defect density, reduces charge scattering and leakage channels; the low-temperature annealing and gradient passivation process improves the interface stability and electric field uniformity, and inhibits surface leakage under high voltage.

The surfaces of epitaxial source and drain regions of NMOS (n-type metal-oxide-semiconductor) transistors are heavily doped with an n-type chalcogen (e.g., tellurium, selenium, sulfur) to overcome the limitations of low-ionization-energy n-type dopants (e.g., phosphorus, arsenic, antimony) on free electron concentrations due to Fermi-level pinning. The chalcogen can be introduced into the source and drain regions by diffusion from a chalcogen-rich metal contact layer or by chemical vapor deposition (CVD) processes in which a chalcogen precursor flows over the source and drain regions after its formation. In some embodiments, the CVD process may involve silicon and chalcogen precursors flowing over the surface of the source and drain regions to form a thin layer of silicon heavily doped with a chalcogen.

Contacts for solar cells and other optoelectronic devices are provided. Embodiments described herein take advantage of the surface Fermi level pinning effect to build an electrical field inside of a semiconductor to extract or inject carriers for solar cells, photodetectors, and light-emitting device applications. For example, n-type or p-type two-dimensional (2D) materials can be used in contact with an n-type semiconductor to form a “p-region” so that a p-n junction, or an i-n or n-n+ junction can be constructed. Similarly, n-type or p-type 2D materials can be used in contact with a p-type semiconductor to form an “n-region” so that an n-p junction, or an i-p or p-p+ junction can be constructed. These structures can provide sufficiently high electrical field inside the semiconductor to extract photogenerated carriers in solar cells and photodetectors or inject minority carriers for light-emitting devices.

The invention discloses a SnS-WSe2 contact construction method based on thermal evaporation and application, and belongs to the field of two-dimensional semiconductor devices and contact engineering, SnS is deposited on a two-dimensional semiconductor WSe2 through a thermal evaporation process by taking Co as a stabilizer under the conditions of high vacuum and low-rate deposition, and a semiconductor-semiconductor Van der Waals interface is formed. A metal-induced interstitial state is effectively inhibited by utilizing the semiconductor property of SnS and the characteristic that the state density in a forbidden band is close to zero; meanwhile, the low-melting-point characteristic is beneficial for obtaining a clean contact interface and reducing a defect-induced gap state, so that Fermi level pinning is remarkably weakened, and near-zero hole injection barrier and ideal ohmic contact are realized. Compared with common high-work-function metal contact, efficient hole injection and low contact resistance can be achieved without additional doping treatment, the technological process is simple, the method is compatible with an existing micro-nano machining technology, and the method is suitable for integration of a high-performance two-dimensional p-FET and an extensible two-dimensional CMOS.

The invention discloses an adaptive contact resistance compensation MoS2 field effect transistor structure, and relates to the technical field of MoS2 field effect transistors. The compensation electrode applies optimized bias voltage under accurate regulation and control of the feedback control circuit, and the ultrathin interface modification layer effectively modulates the energy band structure of the MoS2 channel layer, so that the Schottky barrier height and the interface state density at the contact interface between the source electrode and the MoS2 channel layer and between the drain electrode and the MoS2 channel layer can be reduced, carriers can be injected and extracted more efficiently, and the performance of the device is improved. The current carrier injection bottleneck caused by Fermi level pinning in the traditional MoS2FET is effectively overcome; the contact resistance is greatly reduced, ohmic loss on a source-drain path is directly reduced, the working power consumption of the device is reduced, the contact resistance is lower, the carrier injection / extraction process is more efficient, the time required for establishing and dissipating the channel carrier concentration is shortened, and the switching speed of the device is effectively improved.

The application relates to a preparation method of a NiGe / n-Ge Schottky diode. The method comprises the following steps: taking a Ge sheet as a substrate and pre-treating; growing an isolation layer on the Ge sheet, performing photoetching to form a pattern, and then performing photoetching once; sequentially evaporating Al and Ni, and then removing the metal not in the pattern; annealing, removing the excessive Ni, and evaporating positive and negative electrodes. The method can effectively relieve the Fermi level pinning effect, reduce the NiGe / n-Ge Schottky barrier height, and make the NiGe maintain thermal stability at 400 DEG C to 600 DEG C.

The application discloses a SnS-WSe2 contact construction method based on thermal evaporation and application, belongs to the field of two-dimensional semiconductor devices and contact engineering, and under the condition of high vacuum and low rate deposition, SnS is deposited on two-dimensional semiconductor WSe2 by using Co as a stabilizer through a thermal evaporation process to form a semiconductor-semiconductor van der Waals interface. The semiconductor property of SnS and the near-zero state density in the band gap are utilized to effectively inhibit metal-induced gap states; meanwhile, the low melting point property of SnS is beneficial to obtain a clean contact interface and reduce defect-induced gap states, thereby significantly weakening Fermi level pinning, realizing a near-zero hole injection barrier and ideal ohmic contact. Compared with commonly used high work function metal contact, the application can realize efficient hole injection and low contact resistance without additional doping treatment, the process flow is simple, compatible with the existing micro-nano processing technology, and suitable for high-performance two-dimensional p-FET and scalable two-dimensional CMOS integration.

The surfaces of NMOS (n-type metal-oxide-semiconductor) transistor epitaxial source and drain regions are heavily doped with an n-type chalcogen (e.g., tellurium, selenium, sulfur) to overcome the limitations of low-ionization energy n-type dopants (e.g., phosphorous, arsenic, antimony) to free-electron concentrations due to Fermi-level pinning. The chalcogen can be introduced to the source or drain region surfaces by diffusion from a chalcogen-rich metal contact layer or by chemical vapor deposition processes in which a chalcogen precursor flows over the source and drain regions after they are formed. In some embodiments, the chemical vapor deposition process can comprise silicon and chalcogen precursors flowing over the source and drain region surfaces to form a thin layer of silicon highly doped with a chalcogen.